NDLI: On applying incremental satisfiability to delay fault testing

Content Provider	IEEE Xplore Digital Library
Author	Joonyoung Kim Whittemore, J. Marques-Silva, J.P. Sakallah, K.
Copyright Year	2000
Description	Author affiliation: Michigan Univ., MI, USA (Joonyoung Kim)
Abstract	The Boolean satisfiability problem (SAT) has various applications in electronic design automation (EDA) fields such as testing, timing analysis and logic verification. SAT has been typically applied to EDA as follows: (1) formulation of the given problem as a SAT instance (2) solution of the SAT instance. In this paper we present a method to simultaneously solve several closely related SAT instances using incremental satisfiability (ISAT). In ISAT, the decision sequence made for a "prefix" function is used to solve another set of functions which have a number of new constraints (extensions) added to the prefix function. Our experiments show that we can achieve significant gains in total runtime when we use this methodology as opposed to resetting the decision sequences and solving each instance from scratch. Application of ISAT to delay fault testing is presented by formulating incremental path sensitization as an ISAT problem. Non-robust tests for the combinational portion of ISCAS 89 circuits are generated using this method.
Starting Page	380
Ending Page	384
File Size	157719
Page Count	5
File Format	PDF
ISBN	0769505376
DOI	10.1109/DATE.2000.840299
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2000-03-30
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Delay Electronic design automation and methodology Circuit testing Circuit faults Logic testing Electronic equipment testing Automatic testing Timing Logic design Boolean functions
Content Type	Text
Resource Type	Article

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