NDLI: Development of a simultaneously threaded multi-core processor

Content Provider	IEEE Xplore Digital Library
Author	Zaghloul, S.S. Mudawar, M. Darwish, M.G.
Copyright Year	2005
Description	Author affiliation: SISCO Programs, American Univ. in Cairo (Zaghloul, S.S.)
Abstract	Simultaneous multithreading (SMT) is becoming one of the major trends in the design of future generations of microarchitectures. Its key strength comes from its ability to exploit both thread-level and instruction-level parallelism; it uses hardware resources efficiently. Nevertheless, SMT has its limitations: contention between threads may cause conflicts; lack of scalability, additional pipeline stages, and inefficient handling of long latency operations. Alternatively, chip multiprocessors (CMP) are highly scalable and easy to program. On the other hand, they are expensive and suffer from cache coherence and memory consistency problems. This paper proposes a microarchitecture that exploits parallelism at instruction, thread, and processor levels. It merges both concepts of SMT and CMP. Like CMP, multiple cores are used on a single chip. Hardware resources are replicated in each core except for the secondary-level cache which is shared among all cores. The processor applies the SMT technique within each core to make full use of available hardware resources. Moreover, the communication overhead is reduced due to the inter-independence between cores. Results show that the proposed microarchitecture outperforms both SMT and CMP. In addition, resources are more evenly distributed among running threads
Starting Page	913
Ending Page	927
File Size	2613396
Page Count	15
File Format	PDF
ISBN	0780392701
DOI	10.1109/ITICT.2005.1609676
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2005-12-05
Publisher Place	Egypt
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Chip Multithreading Multicore processing Surface-mount technology Pipelines Chip Multiprocessors Throughput Yarn Delay Microarchitecture Multithreading Simultaneous Multithreading Parallel processing Hardware Parallel Architecture
Content Type	Text
Resource Type	Article

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