NDLI: PACO: Fast average-performance estimation for time-randomized caches

Content Provider	IEEE Xplore Digital Library
Author	Milutinovic, S. Quinones, E. Abella, J. Cazorla, F.J.
Copyright Year	2015
Description	Author affiliation: Barcelona Supercomput. Center, Barcelona, Spain (Quinones, E.; Abella, J.; Cazorla, F.J.) \|\| Univ. Politec. de Catalunya, Barcelona, Spain (Milutinovic, S.)
Abstract	Probabilistic timing analysis is a powerful approach to derive worst-case execution time (WCET) estimates, as needed in safety-critical systems, in the presence of high-performance hardware features (e.g., caches). To that end, the timing behavior of certain hardware resources, such as caches, is randomized. Time-randomized (TR) caches allow deriving hit/miss probabilities for each access and probabilistic WCET estimates for the overall program. However, the analysis of the average performance of TR caches, which is needed for lowly-critical high-performance tasks in mixed-criticality environments, has been neglected. So far, average performance of a TR cache can only be analyzed through simulation, whose accuracy strongly depends on carrying a large number of simulations. In this paper we address this challenge by proposing PACO, an accurate analytical approach to estimate cache hit/miss probabilities of full applications, parts of them and individual cache accesses at low cost for a wide variety of TR cache hierarchies and setups.
Starting Page	1
Ending Page	6
File Size	341962
Page Count	6
File Format	PDF
ISBN	9781479980529
DOI	10.1145/2744769.2744886
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2015-06-08
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Association for Computing Machinery, Inc. (ACM)
Subject Keyword	Approximation methods Accuracy Probabilistic logic Computational modeling Context Timing Benchmark testing
Content Type	Text
Resource Type	Article

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
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