NDLI: Domain-wall memory buffer for low-energy NoCs

Content Provider	IEEE Xplore Digital Library
Author	Kline, D. Haifeng Xu Melhem, R. Jones, A.K.
Copyright Year	2015
Description	Author affiliation: Comput. Eng., Univ. of Pittsburgh, Pittsburgh, PA, USA (Kline, D.) \|\| Comput. Sci., Univ. of Pittsburgh, Pittsburgh, PA, USA (Melhem, R.) \|\| Electr. & Comput. Eng, Univ. of Pittsburgh, Pittsburgh, PA, USA (Haifeng Xu; Jones, A.K.)
Abstract	Networks-on-chip (NoCs) have become a leading energy consumer in modern multi-core processors, with a considerable portion of this energy originating from the large number of virtual channel (FIFO) buffers. While emerging memories have been considered for many architectural components such as caches, the asymmetric access properties and relatively small size of network-FIFOs compared to the required peripheral circuitry has led to few such replacements proposed for NoCs. In this paper, we propose control schemes that leverage the “shift-register” nature of spintronic domain-wall memory (DWM) to replace conventional memory buffers for the NoC. Our results indicate that the best shift-based scheme utilizes a dual-nanowire approach to ensure that reads and writes can be more effectively aligned with access ports for simultaneous access in the same cycle. Our approach provides a 2.93X speedup over a DWM buffer using a traditional FIFO memory control scheme with a 1.16X savings in energy. Compared to a SRAM-FIFO it exhibits an 8% message latency degradation versus a 56% energy reduction. The resulting approach achieves a 53% reduction in energy delay product compared to SRAM and a 42% reduction in energy delay product versus STT-MRAM.
Starting Page	1
Ending Page	6
File Size	595807
Page Count	6
File Format	PDF
ISBN	9781479980529
DOI	10.1145/2744769.2744826
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2015-06-08
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Association for Computing Machinery, Inc. (ACM)
Subject Keyword	Random access memory Delays Magnetic heads Arrays Multicore processing Shift registers FIFOs Network-on-chip Domain-wall Memory
Content Type	Text
Resource Type	Article

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