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| Content Provider | IEEE Xplore Digital Library |
|---|---|
| Author | Ke Zhong Dutt, S. |
| Copyright Year | 2002 |
| Description | Author affiliation: Dept. of Electr. & Comput. Eng., Illinois Univ., Chicago, IL, USA (Ke Zhong; Dutt, S.) |
| Abstract | This paper addresses the problem of tackling multiple constraints simultaneously during a partitioning driven placement (PDP) process, where a larger solution space is available for constraint-satisfying optimization compared to post-placement methods. A general methodology of multi-constraint satisfaction that balances violation correction and primary optimization is presented. A number of techniques are introduced to ensure its convergence and enhance its solution search capability with intermediate relaxation. Application of our approach to congestion control modeled as pin density and external net distribution balance constraints shows it effectively reduces overall congestion by 14.3% and improves chip area by 8.9%, with reasonable running time and only 1.6% increase in wire length. As far as we know, this is the first time an approach to congestion reduction during placement optimization produced good congestion improvement with very small wire length increase. |
| Sponsorship | ACM EDA Consortium IEEE SSCS |
| Starting Page | 854 |
| Ending Page | 859 |
| File Size | 861275 |
| Page Count | 6 |
| File Format | |
| ISBN | 1581134614 |
| ISSN | 0738100X |
| DOI | 10.1109/DAC.2002.1012741 |
| Language | English |
| Publisher | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Publisher Date | 2002-06-10 |
| Publisher Place | USA |
| Access Restriction | Subscribed |
| Rights Holder | Association for Computing Machinery, Inc. (ACM) |
| Subject Keyword | Constraint optimization Programmable logic arrays Wire Circuits Partitioning algorithms Permission Crosstalk Timing Space exploration Algorithm design and analysis |
| Content Type | Text |
| Resource Type | Article |
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