NDLI: Dynamic and leakage power reduction in MTCMOS circuits using an automated efficient gate clustering technique

Content Provider	IEEE Xplore Digital Library
Author	Anis, M. Areibi, S. Mahmoud, M. Elmasry, M.
Copyright Year	2002
Description	Author affiliation: Dept. of Electr. & Comput. Eng., Waterloo Univ., Ont., Canada (Anis, M.; Areibi, S.; Mahmoud, M.; Elmasry, M.)
Abstract	Reducing power dissipation is one of the most principle subjects in VLSI design today. Scaling causes subthreshold leakage currents to become a large component of total power dissipation. This paper presents two techniques for efficient gate clustering in MTCMOS circuits by modeling the problem via Bin-Packing (BP) and Set-Partitioning (SP) techniques. An automated solution is presented, and both techniques are applied to six benchmarks to verify functionality. Both methodologies offer significant reduction in both dynamic and leakage power over previous techniques during the active and standby modes respectively. Furthermore, the SP technique takes the circuit's routing complexity into consideration which is critical for Deep Sub-Micron (DSM) implementations. Sufficient performance is achieved, while significantly reducing the overall sleep transistors' area. Results obtained indicate that our proposed techniques can achieve on average 90% savings for leakage power and 15% savings for dynamic power.
Sponsorship	ACM EDA Consortium IEEE SSCS
Starting Page	480
Ending Page	485
File Size	658433
Page Count	6
File Format	PDF
ISBN	1581134614
ISSN	0738100X
DOI	10.1109/DAC.2002.1012673
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2002-06-10
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Association for Computing Machinery, Inc. (ACM)
Subject Keyword	Circuits Threshold voltage CMOS technology Resistors Power dissipation Subthreshold current Degradation Permission Design engineering Power engineering and energy
Content Type	Text
Resource Type	Article

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