NDLI: A reconfigurable FPGA-based readback signal generator for hard-drive read channel simulator

Content Provider	IEEE Xplore Digital Library
Author	Jinghuan Chen Jaekyun Moon Bazargan, K.
Copyright Year	2002
Description	Author affiliation: Dept. of Electr. & Comput. Eng., Minnesota Univ., USA (Jinghuan Chen; Jaekyun Moon; Bazargan, K.)
Abstract	A hard disk readback signal generator designed to provide noise-corrupted signals to a channel simulator has been implemented on a Xilinx Virtex/spl trade/E FPGA device. The generator simulates pulses sensed by read heads in hard drives. All major distortion and noise processes, such as intersymbol interference, transition noise, electronics noise, head and media nonlinearity, intertrack interference, and write timing error, can be generated according to the statistics and parameters defined by the user. Reconfigurable implementation enables an update of the signal characteristics in runtime. The user also has the flexibility to choose from a set of bitstreams to simulate particular combinations of noise and distortion. Such customized restructuring helps reduce the area consumption and hence virtually increase the capacity of the FPGA device. The time to generate the readback signals has been reduced by four orders compared to its software counterpart.
Sponsorship	ACM EDA Consortium IEEE SSCS
Starting Page	349
Ending Page	354
File Size	744839
Page Count	6
File Format	PDF
ISBN	1581134614
ISSN	0738100X
DOI	10.1109/DAC.2002.1012648
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2002-06-10
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Association for Computing Machinery, Inc. (ACM)
Subject Keyword	Signal generators Noise generators Field programmable gate arrays Intersymbol interference Hard disks Signal design Pulse generation Timing Error analysis Runtime
Content Type	Text
Resource Type	Article

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
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