NDLI: False timing path identification using ATPG techniques and delay-based information

Content Provider	IEEE Xplore Digital Library
Author	Jing Zeng Abadir, M. Abraham, J.
Copyright Year	2002
Description	Author affiliation: High Performance Tools & Methodology, Motorola Inc., Austin, TX, USA (Jing Zeng; Abadir, M.)
Abstract	A well-known problem in timing verification of VLSI circuits using static timing analysis tools is the generation of false timing paths. This leads to a pessimistic estimation of the processor speed and wasted engineering effort spent optimizing unsensitizable paths. Earlier results have shown how ATPG techniques can be used to identify false paths efficiently, as well as how to bridge the gap between the physical design on which the static timing analysis is based and the test view on which ATPG technique is applied to identify false paths. In this paper, we will demonstrate efficient techniques to identify more false timing paths by utilizing information from an ordered list of timing paths according to the delay information. More than 10% of additional false timing paths out of the total timing paths analyzed are identified compared to earlier results on the MPC7455, a Motorola processor executing to the PowerPC/spl trade/ instruction set architecture.
Sponsorship	ACM EDA Consortium IEEE SSCS
Starting Page	562
Ending Page	565
File Size	467973
Page Count	4
File Format	PDF
ISBN	1581134614
ISSN	0738100X
DOI	10.1109/DAC.2002.1012688
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2002-06-10
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Association for Computing Machinery, Inc. (ACM)
Subject Keyword	Timing Automatic test pattern generation Delay Algorithm design and analysis Performance analysis Very large scale integration Permission Iterative algorithms Bridge circuits Testing
Content Type	Text
Resource Type	Article

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1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
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