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| Content Provider | IEEE Xplore Digital Library |
|---|---|
| Author | Bajdechi, O. Gielen, G. Huijsing, J.H. |
| Copyright Year | 2002 |
| Description | Author affiliation: Delft Univ. of Technol., Netherlands (Bajdechi, O.) |
| Abstract | An algorithm for architecture-level exploration of /spl Delta//spl Sigma/ ADC design space is presented. The algorithm finds an optimal solution by exhaustively exploring both single-loop and cascaded architectures, with single-bit or multi-bit quantizer, for a range of oversampling ratios. A fast filter-level step evaluates the performance of all loop-filter topologies and passes the accepted solutions to the architecture-level optimization step which maps the filters on feasible architectures and evaluates their performance. The power consumption of each accepted architecture is estimated and the best top-ten solutions in terms of the ratio of peak SNDR versus power consumption are further optimized for yield. Experimental results for two different design targets are presented. They show that previously published solutions are among the best architectures for a given target but that better solutions can be designed. |
| Sponsorship | ACM EDA Consortium IEEE SSCS |
| Starting Page | 443 |
| Ending Page | 448 |
| File Size | 609009 |
| Page Count | 6 |
| File Format | |
| ISBN | 1581134614 |
| ISSN | 0738100X |
| DOI | 10.1109/DAC.2002.1012666 |
| Language | English |
| Publisher | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Publisher Date | 2002-06-10 |
| Publisher Place | USA |
| Access Restriction | Subscribed |
| Rights Holder | Association for Computing Machinery, Inc. (ACM) |
| Subject Keyword | Space exploration Space technology Energy consumption Computer architecture Topology Computer applications Design automation Permission CMOS technology Analytical models |
| Content Type | Text |
| Resource Type | Article |
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