NDLI: A flexible accelerator for Layer 7 networking applications

Content Provider	IEEE Xplore Digital Library
Author	Memik, G. Mangione-Smith, W.H.
Copyright Year	2002
Description	Author affiliation: Dept. of Electr. Eng., California Univ., Los Angeles, CA, USA (Memik, G.; Mangione-Smith, W.H.)
Abstract	In this paper, we present a flexible accelerator designed for networking applications. The accelerator can be utilized efficiently by a variety of Network Processor designs. Most Network Processors employ hardware accelerators for implementing key tasks. New applications require new tasks, such as pattern matching, to be performed on the packets in real-time. Using our proposed accelerator, we have implemented several such tasks and measured their performance. Specifically, the accelerator achieves 25-fold improvement on the performance of pattern matching, and 10-fold improvement for tree lookup, over optimized software solutions. Since the accelerator is used for different tasks, the hardware requirements are small compared to an accelerator group that implements the same set of tasks. We also present accurate analytic models to estimate the execution time of these networking tasks.
Sponsorship	ACM EDA Consortium IEEE SSCS
Starting Page	646
Ending Page	651
File Size	651577
Page Count	6
File Format	PDF
ISBN	1581134614
ISSN	0738100X
DOI	10.1109/DAC.2002.1012704
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2002-06-10
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Association for Computing Machinery, Inc. (ACM)
Subject Keyword	Application software Hardware Pattern matching Algorithm design and analysis Software performance Arithmetic Application specific integrated circuits Permission Process design Logic
Content Type	Text
Resource Type	Article

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