NDLI: A fast, inexpensive and scalable hardware acceleration technique for functional simulation

Content Provider	IEEE Xplore Digital Library
Author	Cadambi, S. Mulpuri, C.S. Ashar, P.N.
Copyright Year	2002
Description	Author affiliation: C&C Res. Labs., NEC, Princeton, NJ, USA (Cadambi, S.; Mulpuri, C.S.; Ashar, P.N.)
Abstract	The key attributes of our approach are high-performance, low-cost, scalability and low turn-around-time (TAT). We achieve speedups between 25 and 2000/spl times/ over zero delay event-driven simulation and between 75 and 1000/spl times/ over cycle-based simulation on benchmark and industrial circuits while maintaining the cost, scalability and TAT advantages of simulation. Owing to these attributes, we believe that such an approach has potential for very wide deployment as replacement or enhancement for existing simulators. Our technology relies on a VLIW-like virtual simulation processor (SimPLE) mapped to a single FPGA on an off-the-shelf PCI-board. Primarily responsible for the speed are (i) parallelism in the processor architecture (ii) high pin count on the FPGA enabling large instruction bandwidth and (iii) high speed (124 MHz on Xilinx Virtex-II) single-FPGA implementation of the processor with regularity driven efficient place and route. Companion to the processor is the very fast SimPLE compiler which achieves compilation rates of 4 million gates/hour. In order to simulate the netlist, the compiled instructions are streamed through the FPGA, along with the simulation vectors. This architecture plugs in naturally into any existing HDL simulation environment.
Sponsorship	ACM EDA Consortium IEEE SSCS
Starting Page	570
Ending Page	575
File Size	706946
Page Count	6
File Format	PDF
ISBN	1581134614
ISSN	0738100X
DOI	10.1109/DAC.2002.1012690
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2002-06-10
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Association for Computing Machinery, Inc. (ACM)
Subject Keyword	Hardware Acceleration Circuit simulation Discrete event simulation Field programmable gate arrays Scalability Delay Costs Bandwidth Plugs
Content Type	Text
Resource Type	Article

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