NDLI: Diagnosis Framework for Locating Failed Segments of Path Delay Faults

Content Provider	IEEE Xplore Digital Library
Author	Ying-Yen Chen Jing-Jia Liou
Copyright Year	1993
Abstract	Diagnosis tools can be used to speed up the process for finding the root causes of functional or performance problems in a VLSI circuit. In this paper, we propose a method to locate possible segments that cause extra delays on circuit paths. We use the delay bounds of the tested paths to build linear constraints. By guiding the solutions of the linear constraints solved by a linear programming solver, we can identify segments with extra delays. Also, with the ranks of segment delays, we can prioritize the search for possible locations of failed segments. Besides, we also propose to reduce the search space by identifying indistinguishable segments. Essentially, we cannot separate segments in the same category no matter which segments have faults. This approach greatly increases the efficiency of the diagnosis process. Three main features of the proposed method are that: 1) it does not assume any delay fault model; 2) it derives diagnosis results directly from test data; and 3) it is able to diagnose failures caused by multiple delay defects. These features make our proposed method more realistic on solving the real problems occurring in the manufacturing process. In the experimental results, for most cases of injecting 5% of the longest path delay, the probabilities are over 90% for locating faulty segments within the list of top-ten suspects, and the average rankings, that is often referred to as first hit rank (FHR), which is defined as the rank of the first hit of the defect in the ranking list, are among the top five suspect locations for single fault injection. In the experimental results of multiple faults injection, the average FHRs are also lower than 5 for all cases of injecting 1% of the longest path delay.
Sponsorship	IEEE Computer Society Association for Computing Machinery (ACM)/SIGDA IEEE Computer Society Technical Committee on Design Automation
Starting Page	755
Ending Page	765
Page Count	11
File Size	728358
File Format	PDF
ISSN	10638210
Volume Number	16
Issue Number	6
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2008-06-01
Publisher Place	U.S.A.
Access Restriction	One Nation One Subscription (ONOS)
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Fault diagnosis Circuit faults Timing Delay effects Clocks Very large scale integration Automatic test pattern generation Automatic testing Circuit testing Linear programming timing analysis Automatic test equipment (ATE) automatic test pattern generation (ATPG) built-in self testing (BIST) delay diagnosis delay testing fault model
Content Type	Text
Resource Type	Article
Subject	Electrical and Electronic Engineering Software Hardware and Architecture

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