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Content Provider | IEEE Xplore Digital Library |
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Author | Tun Li Dan Zhu Sikun Li Yang Guo |
Copyright Year | 2013 |
Description | Author affiliation: Sch. of Comput., Nat. Univ. of Defense Technol., Changsha, China (Tun Li; Dan Zhu; Sikun Li; Yang Guo) |
Abstract | Soft errors have become a critical challenge as a result of technology scaling. However, to evaluate the influence of soft errors in flip-flop (FF) on the failure of circuit is a hard verification problem. Here, we proposed a novel flip-flop soft error failure rate analysis methodology using sequential equivalence checking (SEC) and taking the application behaviors into consideration, which combines the advantage of formal techniques based approaches in completeness and the advantage of application behaviors in accuracy in differentiating vulnerability of FFs. As a result, all the FFs in a circuit are sorted by their failure rates and designers can use this information to perform optimal hardening of selected sequential components against soft errors. Experimental results on an implementation of a SpaceWire end node and the set of the largest ISCAS'89 benchmark sequential circuits demonstrate the efficiency of our approach. Case study on an instruction decoder of a practical 32 bits microprocessor shows the applicable of our methodology. |
Starting Page | 608 |
Ending Page | 613 |
File Size | 203184 |
Page Count | 6 |
File Format | |
ISBN | 9781467330299 |
ISSN | 21536961 |
e-ISBN | 9781467330305 |
DOI | 10.1109/ASPDAC.2013.6509665 |
Language | English |
Publisher | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
Publisher Date | 2013-01-22 |
Publisher Place | Japan |
Access Restriction | Subscribed |
Rights Holder | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
Subject Keyword | Circuit faults Integrated circuit modeling Computational modeling Silicon Robustness Vectors Benchmark testing Application Soft-error Failure rate analysis Sequential equivalence checking |
Content Type | Text |
Resource Type | Article |
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