NDLI: An ultra-compact virtual source FET model for deeply-scaled devices: Parameter extraction and validation for standard cell libraries and digital circuits

Content Provider	IEEE Xplore Digital Library
Author	Li Yu Mysore, O. Lan Wei Daniel, L. Antoniadis, D. Elfadel, I. Boning, D.
Copyright Year	2013
Description	Author affiliation: Masdar Inst. of Sci. & Technol., Abu Dhabi, United Arab Emirates (Elfadel, I.; Boning, D.) \|\| Massachusetts Inst. of Technol., Cambridge, MA, USA (Li Yu; Mysore, O.; Lan Wei; Daniel, L.; Antoniadis, D.)
Abstract	In this paper, we present the first validation of the virtual source (VS) charge-based compact model for standard cell libraries and large-scale digital circuits. With only a modest number of physically meaningful parameters, the VS model accounts for the main short-channel effects in nanometer technologies. Using a novel DC and transient parameter extraction methodology, the model is verified with simulated data from a well-characterized, industrial 40-nm bulk silicon model. The VS model is used to fully characterize a standard cell library with timing comparisons showing less than 2.7% error with respect to the industrial design kit. Furthermore, a 1001-stage inverter chain and a 32-bit ripple-carry adder are employed as test cases in a vendor CAD environment to validate the use of the VS model for large-scale digital circuit applications. Parametric Vdd sweeps show that the VS model is also ready for usage in low-power design methodologies. Finally, runtime comparisons have shown that the use of the VS model results in a speedup of about 7.6×.
Starting Page	521
Ending Page	526
File Size	752272
Page Count	6
File Format	PDF
ISBN	9781467330299
ISSN	21536961
e-ISBN	9781467330305
DOI	10.1109/ASPDAC.2013.6509649
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2013-01-22
Publisher Place	Japan
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Solid modeling Integrated circuit modeling Mathematical model Semiconductor device modeling Logic gates Timing Capacitance
Content Type	Text
Resource Type	Article

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1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
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