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Content Provider | IEEE Xplore Digital Library |
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Author | Ikeno, R. Maruyama, T. Iizuka, T. Komatsu, S. Ikeda, M. Asada, K. |
Copyright Year | 2013 |
Description | Author affiliation: e-Shuttle, Inc., Japan (Maruyama, T.) || Dept. of Electr. Eng. & Inf. Syst., Univ. of Tokyo, Tokyo, Japan (Iizuka, T.) || VLSI Design & Educ. Center (VDEC), Univ. of Tokyo, Tokyo, Japan (Ikeno, R.; Komatsu, S.; Ikeda, M.; Asada, K.) |
Abstract | Character projection (CP) is a high-speed mask-less exposure technique for electron-beam direct writing (EBDW). In CP exposure of VIA layers, higher throughput is realized if more VIAs are exposed in each EB shot, but it will result in huge number of VIA characters required for arbitrary VIA placement. We adopt one-dimensional VIA array as the basic CP character architecture to increase VIA numbers in an EB shot while saving the stencil area by superposed character arrangement. CP throughput is further improved by layout constraints for VIA placement in detail routing phase. Our experimental results give estimated EB shot counts less than 174G shot/wafer in 14nm technologies. |
Starting Page | 255 |
Ending Page | 260 |
File Size | 185896 |
Page Count | 6 |
File Format | |
ISBN | 9781467330299 |
ISSN | 21536961 |
e-ISBN | 9781467330305 |
DOI | 10.1109/ASPDAC.2013.6509605 |
Language | English |
Publisher | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
Publisher Date | 2013-01-22 |
Publisher Place | Japan |
Access Restriction | Subscribed |
Rights Holder | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
Subject Keyword | Layout Encoding Computer architecture Microprocessors Throughput Routing Apertures |
Content Type | Text |
Resource Type | Article |
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