NDLI: A 3Gb/s $2.08mm^{2}$ 100b error-correcting BCH decoder in 0.13µm CMOS process

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2014 19th Asia and South Pacific Design Automation Conference (ASP-DAC)

2013 18th Asia and South Pacific Design Automation Conference (ASP-DAC)

Equivalent circuit model extraction for interconnects in 3D ICs

Unconditionally stable explicit method for the fast 3-D simulation of on-chip power distribution network with through silicon via

Signal integrity modeling and measurement of TSV in 3D IC

Power distribution network modeling for 3-D ICs with TSV arrays

A case for wireless 3D NoCs for CMPs

Deflection routing in 3D Network-on-Chip with TSV serialization

MD: Minimal path-based fault-tolerant routing in on-Chip Networks

A dynamic stream link for efficient data flow control in NoC based heterogeneous MPSoC

On real-time STM concurrency control for embedded software with improved schedulability

Schedule integration for time-triggered systems

Online estimation of the remaining energy capacity in mobile systems considering system-wide power consumption and battery characteristics

WUCC: Joint WCET and Update Conscious Compilation for cyber-physical systems

A 40-nm 144-mW VLSI processor for real-time 60-kWord continuous speech recognition

A 24.5–53.6pJ/pixel 4320p 60fps H.264/AVC intra-frame video encoder chip in 65nm CMOS

A low power multimedia processor implementing dynamic voltage and frequency scaling technique

A 40-nm 0.5-V 12.9-pJ/Access 8T SRAM using low-power disturb mitigation technique

A physical unclonable function chip exploiting load transistors' variation in SRAM bitcells

Over 10-times high-speed, energy efficient 3D TSV-integrated hybrid ReRAM/MLC NAND SSD by intelligent data fragmentation suppression

Highly reliable solid-state drives (SSDs) with error-prediction LDPC (EP-LDPC) architecture and error-recovery scheme

A 3Gb/s $2.08mm^{2}$ 100b error-correcting BCH decoder in 0.13µm CMOS process

A 6.72-Gb/s, 8pJ/bit/iteration WPAN LDPC decoder in 65nm CMOS

A 7.5Gb/s referenceless transceiver for UHDTV with adaptive equalization and bandwidth scanning technique in 0.13µm CMOS process

A 12.5Gb/s/link non-contact multi drop bus system with impedance-matched Transmission Line Couplers and Dicode partial-response channel transceivers

315MHz OOK transceiver with 38-µW receiver and 36-µW transmitter in 40-nm CMOS

A full 4-channel 60 GHz direct-conversion transceiver

A sub-harmonic injection-locked frequency synthesizer with frequency calibration scheme for use in 60GHz TDD transceivers

A fractional-N harmonic injection-locked frequency synthesizer with 10MHz–6.6GHz quadrature outputs for software-defined radios

A ring-VCO-based sub-sampling PLL CMOS circuit with 0.73 ps jitter and 20.4 mW power consumption

Design of a clock jitter reduction circuit using gated phase blending between self-delayed clock edges

A 25-Gb/s LD driver with area-effective inductor in a 0.18-µm CMOS

A regulated charge pump with low-power integrated optimum power point tracking algorithm for indoor solar energy harvesting

A low voltage buck DC-DC converter using on-chip gate boost technique in 40nm CMOS

A 0.35-0.8V 8b 0.5-35MS/s 2bit/step extremely-low power SAR ADC

Thermal management for dependable on-chip systems

Dependable VLSI Platform using Robust Fabrics

Variability-aware memory management for nanoscale computing

MIXSyn: An efficient logic synthesis methodology for mixed XOR-AND/OR dominated circuits

Optimizing multi-level combinational circuits for generating random bits

Improving the mapping of reversible circuits to quantum circuits using multiple target lines

I-LUTSim: An iterative look-up table based thermal simulator for 3-D ICs

Compact nonlinear thermal modeling of packaged integrated systems

A multilevel ℌ-matrix-based approximate matrix inversion algorithm for vectorless power grid verification

Realization of frequency-domain circuit analysis through random walk

A separation and minimum wire length constrained maze routing algorithm under nanometer wiring rules

An ILP-based automatic bus planner for dense PCBs

Layer minimization in escape routing for staggered-pin-array PCBs

Network flow modeling for escape routing on staggered pin arrays

A clique-based approach to find binding and scheduling result in flow-based microfluidic biochips

Control synthesis for the flow-based microfluidic large-scale integration biochips

A network-flow based valve-switching aware binding algorithm for flow-based microfluidic biochips

Design and verification tools for continuous fluid flow-based microfluidic devices

Optimal partition with block-level parallelization in C-to-RTL synthesis for streaming applications

Multi-mode pipelined MPSoCs for streaming applications

Network simplex method based Multiple Voltage Scheduling in Power-efficient High-level synthesis

VISA synthesis: Variation-aware Instruction Set Architecture synthesis

L-shape based layout fracturing for e-beam lithography

High-throughput electron beam direct writing of VIA layers by character projection using character sets based on one-dimensional VIA arrays with area-efficient stencil design

Linear time algorithm to find all relocation positions for EUV defect mitigation

Self-Aligned Double and Quadruple Patterning-aware grid routing with hotspots control

Compiler-assisted refresh minimization for volatile STT-RAM cache

Curling-PCM: Application-specific wear leveling for phase change memory based embedded systems

Selectively protecting error-correcting code for area-efficient and reliable STT-RAM caches

Loadsa: A yield-driven top-down design method for STT-RAM array

Fractal video compression in OpenCL: An evaluation of CPUs, GPUs, and FPGAs as acceleration platforms

High-level synthesis of multiple dependent CUDA kernels on FPGA

The Liquid Metal IP bridge

TRISHUL: A single-pass optimal two-level inclusive data cache hierarchy selection process for real-time MPSoCs

Optimizing translation information management in NAND flash memory storage systems

An adaptive filtering mechanism for energy efficient data prefetching

Cache Capacity Aware Thread Scheduling for Irregular Memory Access on many-core GPGPUs

Optimization of overdrive signoff

Mountain-mover: An intuitive logic shifting heuristic for improving timing slack violating paths

Pulsed-latch ASIC synthesis in industrial design flow

Power optimization for application-specific 3D network-on-chip with multiple supply voltages

Hardware security strategies exploiting nanoelectronic circuits

Can we identify smartphone app by power trace? [Extended abstract for special session]

Secure storage system and key technologies

Mobile user classification and authorization based on gesture usage recognition

Challenges in integration of diverse functionalities on CMOS

3DIC from concept to reality

2.5D design methodology

Design issues in heterogeneous 3D/2.5D integration

Formal verification of distributed controllers using Time-Stamped Event Count Automata

Reliability assessment of safety-relevant automotive systems in a model-based design flow

Sequential dependency and reliability analysis of embedded systems

Processor and DRAM integration by TSV-based 3-D stacking for power-aware SOCs

A flexible fixed-outline floorplanning methodology for mixed-size modules

Optimizing routability in large-scale mixed-size placement

Symmetrical buffered clock-tree synthesis with supply-voltage alignment

BonnCell: Automatic layout of leaf cells

Register and thread structure optimization for GPUs

Real-time partitioned scheduling on multi-core systems with local and global memories

Dynamic thermal management for multi-core microprocessors considering transient thermal effects

BAMSE: A balanced mapping space exploration algorithm for GALS-based manycore platforms

Thermal simulator of 3D-IC with modeling of anisotropic TSV conductance and microchannel entrance effects

A novel cell placement algorithm for flexible TFT circuit with mechanical strain and temperature consideration

Improving energy efficiency for energy harvesting embedded systems

Modeling variability and irreproducibility of nanoelectronic resistive switches for circuit simulation

HS3DPG: Hierarchical simulation for 3D P/G network

Piecewise-polynomial associated transform macromodeling algorithm for fast nonlinear circuit simulation

An ultra-compact virtual source FET model for deeply-scaled devices: Parameter extraction and validation for standard cell libraries and digital circuits

On potential design impacts of electromigration awareness

Provably optimal test cube generation using quantified boolean formula solving

Synthesizing multiple scan chains by cost-driven spectral ordering

A binding algorithm in high-level synthesis for path delay testability

Full exploitation of process variation space for continuous delivery of optimal delay test quality

SMYLE Project: Toward high-performance, low-power computing on manycore-processor SoCs

SMYLEref: A reference architecture for manycore-processor SoCs

SMYLE OpenCL: A programming framework for embedded many-core SoCs

Support tools for porting legacy applications to multicore

Manycore processor for video mining applications

Native simulation of complex VLIW instruction sets using static binary translation and Hardware-Assisted Virtualization

RExCache: Rapid exploration of unified last-level cache

An efficient hybrid synchronization technique for scalable multi-core instruction set simulations

Statistical analysis of BTI in the presence of process-induced voltage and temperature variations

CLASS: Combined logic and architectural soft error sensitivity analysis

Application specified soft error failure rate analysis using sequential equivalence checking techniques

An adaptive current-threshold determination for IDDQ testing based on Bayesian process parameter estimation

DARNS:A randomized multi-modulo RNS architecture for double-and-add in ECC to prevent power analysis side channel attacks

ScanPUF: Robust ultralow-overhead PUF using scan chain

An efficient compression scheme for checkpointing of FPGA-based digital mockups

Maximizing return on investment of a grid-connected hybrid electrical energy storage system

Silicon photonics technology platform for embedded and integrated optical interconnect systems

High-frequency circuit design for 25 Gb/s×4 optical transceiver

Design and application of highly integrated optical switches based on silicon photonics

High performance PIN Ge photodetector and Si optical modulator with MOS junction for photonics-electronics convergence system

Reevaluating the latency claims of 3D stacked memories

Heterogeneous memory management for 3D-DRAM and external DRAM with QoS

Line sharing cache: Exploring cache capacity with frequent line value locality

ShieldUS: A novel design of dynamic shielding for eliminating 3D TSV crosstalk coupling noise

High-density integration of functional modules using monolithic 3D-IC technology

Block-level designs of die-to-wafer bonded 3D ICs and their design quality tradeoffs

Thermal-reliable 3D clock-tree synthesis considering nonlinear electrical-thermal-coupled TSV model

Stacking signal TSV for thermal dissipation in global routing for 3D IC

VFCC: A verification framework of cache coherence using parallel simulation

A computational model for SAT-based verification of hardware-dependent low-level embedded system software

Reviving erroneous stability-based clock-gating using partial Max-SAT

Simplification of C-RTL equivalent checking for fused multiply add unit using intermediate models

Memory access reconstruction based on memory allocation mechanism for source-level simulation of embedded software

Shared cache aware task mapping for WCRT minimization

Scratchpad Memory aware task scheduling with minimum number of preemptions on a single processor

An efficient scheduling algorithm for multiple charge migration tasks in hybrid electrical energy storage systems

Stable backward reachability correction for PLL verification with consideration of environmental noise induced jitter

Performance bound and yield analysis for analog circuits under process variations

Local approximation improvement of trajectory piecewise linear macromodels through Chebyshev interpolating polynomials

Range and bitmask analysis for hardware optimization in high-level synthesis

A gradual scheduling framework for problem size reduction and cross basic block parallelism exploitation in high-level synthesis

Implementing microprocessors from simplified descriptions

Application-specific fault-tolerant architecture synthesis for digital microfluidic biochips

17th Asia and South Pacific Design Automation Conference

16th Asia and South Pacific Design Automation Conference (ASP-DAC 2011)

2010 15th Asia and South Pacific Design Automation Conference (ASP-DAC)

2009 Asia and South Pacific Design Automation Conference

2008 Asia and South Pacific Design Automation Conference

2007 Asia and South Pacific Design Automation Conference

Asia and South Pacific Conference on Design Automation, 2006.

Proceedings of the ASP-DAC 2005. Asia and South Pacific Design Automation Conference, 2005.

ASP-DAC 2004: Asia and South Pacific Design Automation Conference 2004 (IEEE Cat. No.04EX753)

Proceedings of the ASP-DAC Asia and South Pacific Design Automation Conference, 2003.

Proceedings of ASP-DAC/VLSI Design 2002. 7th Asia and South Pacific Design Automation Conference and 15h International Conference on VLSI Design

Proceedings of the ASP-DAC 2001. Asia and South Pacific Design Automation Conference 2001 (Cat. No.01EX455)

Proceedings 2000. Design Automation Conference. (IEEE Cat. No.00CH37106)

Proceedings of the ASP-DAC '99 Asia and South Pacific Design Automation Conference 1999 (Cat. No.99EX198)

Proceedings of 1998 Asia and South Pacific Design Automation Conference

Proceedings of ASP-DAC '97: Asia and South Pacific Design Automation Conference

Proceedings of ASP-DAC'95/CHDL'95/VLSI'95 with EDA Technofair

A 3Gb/s $2.08mm^{2}$ 100b error-correcting BCH decoder in 0.13µm CMOS process

Content Provider	IEEE Xplore Digital Library
Author	Youngjoo Lee Hoyoung Yoo In-Cheol Park
Copyright Year	2013
Description	Author affiliation: Dept. of Electr. Eng., Korea Adv. Inst. of Sci. & Technol. (KAIST), Daejeon, South Korea (Youngjoo Lee; Hoyoung Yoo; In-Cheol Park)
Abstract	This paper presents a high-throughput BCH decoder that can correct 100 bit-errors. Several optimization methods are proposed to reduce the hardware complexity caused by the large error-correction capability. Based on the proposed methods, an 8-parallel decoder is designed for the (9592, 8192, 100) BCH code, which achieves a decoding throughput of 3Gb/s and occupies $2.08mm^{2}$ in 0.13μm CMOS process.
Starting Page	85
Ending Page	86
File Size	124128
Page Count	2
File Format	PDF
ISBN	9781467330299
ISSN	21536961
e-ISBN	9781467330305
DOI	10.1109/ASPDAC.2013.6509568
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2013-01-22
Publisher Place	Japan
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Decoding Hardware Throughput Complexity theory Polynomials Logic gates Computer architecture
Content Type	Text
Resource Type	Article

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