NDLI: An Approximate Soft Error Reliability Sorting Approach Based on State Analysis of Sequential Circuits

Content Provider	IEEE Xplore Digital Library
Author	Dan Zhu Tun Li Si-kun Li
Copyright Year	2010
Abstract	Soft errors have become a critical challenge as a result of technology scaling. Existing hardening techniques commonly associate prohibitive overhead of performance, area and power. To reach a reliability target at acceptable cost, soft error reliability evaluation of components (gates and flip-flops(FFs)) in a circuit is crucial. In this work, the correlation between the state space of sequential circuits and the soft error vulnerability are analyzed theoretically. And an approximate FF reliability sorting approach based on the circuit state analysis is proposed. It combines the advantage of formal techniques based approaches in completeness and the advantage of simulation based approach in differentiating vulnerability of components, which can help engineers make preliminary vulnerability estimation even when a good workload estimation of the design is unavailable. Experimental results on an implementation of a Space wire end node and several ISCAS’89 benchmark sequential circuits indicate the feasibility and potential scalability of our approach.
Starting Page	209
Ending Page	217
File Size	302032
Page Count	9
File Format	PDF
ISBN	9781424484478
ISSN	15505774
DOI	10.1109/DFT.2010.32
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2010-10-06
Publisher Place	Japan
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Circuit faults Integrated circuit modeling Robustness Computational modeling Strontium Estimation vulnerable state set soft error reliability evaluation
Content Type	Text
Resource Type	Article

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
6	Contents and Copyright Issues	Queries related to content curation and copyright issues	content@ndl.gov.in
7	National Digital Library of India Club (NDLI Club)	Queries related to NDLI Club formation, support, user awareness program, seminar/symposium, collaboration, social media, promotion, and outreach	clubsupport@ndl.gov.in
8	Digital Preservation Centre (DPC)	Assistance with digitizing and archiving copyright-free printed books	dpc@ndl.gov.in
9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in

On Soft Error Immunity of Sequential Circuits

A Fast Analytical Approach to Multi-cycle Soft Error Rate Estimation of Sequential Circuits

A simulation-based soft error estimation methodology for computer systems

Application specified soft error failure rate analysis using sequential equivalence checking techniques

Latency Analysis for Sequential Circuits

Formal modeling and reasoning for reliability analysis

Recovery from Transition Errors in Sequential Circuits

Fast Reliability Analysis Method for Sequential Logic Circuits

On the Reliable Performance of Sequential Adders for Soft Computing

An Approximate Soft Error Reliability Sorting Approach Based on State Analysis of Sequential Circuits

Similar Documents

On Soft Error Immunity of Sequential Circuits

A Fast Analytical Approach to Multi-cycle Soft Error Rate Estimation of Sequential Circuits

A simulation-based soft error estimation methodology for computer systems

Application specified soft error failure rate analysis using sequential equivalence checking techniques

Latency Analysis for Sequential Circuits

Formal modeling and reasoning for reliability analysis

Recovery from Transition Errors in Sequential Circuits

Fast Reliability Analysis Method for Sequential Logic Circuits

On the Reliable Performance of Sequential Adders for Soft Computing

An Approximate Soft Error Reliability Sorting Approach Based on State Analysis of Sequential Circuits