NDLI: Mountain-mover: An intuitive logic shifting heuristic for improving timing slack violating paths

Content Provider	IEEE Xplore Digital Library
Author	Xing Wei Wai-Chung Tang Yu-Liang Wu Sze, C. Alpert, C.
Copyright Year	2013
Description	Author affiliation: Dept. of Comput. Sci. & Eng., Chinese Univ. of Hong Kong, Hong Kong, China (Xing Wei; Wai-Chung Tang; Yu-Liang Wu) \|\| IBM Austin Res. Center, Austin, TX, USA (Sze, C.; Alpert, C.)
Abstract	Based on a simple intuitive notion, in this paper, we propose an efficient post-placement improvement scheme. Based on the given timing slack distribution of a circuit, a corresponding “slack mountain map” can be visualized with peaks representing most violating (negative) slacks and valleys representing non-critical (positive) slacks respectively. Guided by this map, violating paths are eliminated or improved when slack mountains are flattened by applying a local logic perturbation technique (rewiring) iteratively to shift logic resources from critical to non-critical areas. Due to the locality property of the rewiring technique, to better avoid being stuck at local minimums, instead of running rewiring operations from the peak top towards lower areas, we do this local logic shifting starting from “sea areas” (most non-critical) towards peak (most critical) areas. At the end, as the slack map is more flattened, a circuit with slack violations more evenly distributed can be yielded. Comparing to the recent work [1], our experimental results demonstrate that this scheme can obtain a better or comparable delay reduction but with CPU time one order of magnitude smaller.
Starting Page	350
Ending Page	355
File Size	396420
Page Count	6
File Format	PDF
ISBN	9781467330299
ISSN	21536961
e-ISBN	9781467330305
DOI	10.1109/ASPDAC.2013.6509620
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2013-01-22
Publisher Place	Japan
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Wires Logic gates Delays Optimization Engines Central Processing Unit
Content Type	Text
Resource Type	Article

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
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