NDLI: Performance bound and yield analysis for analog circuits under process variations

Content Provider	IEEE Xplore Digital Library
Author	Xue-Xin Liu Palma-Rodriguez, A.A. Rodriguez-Chavez, S. Tan, S.X.-D. Tlelo-Cuautle, E. Yici Cai
Copyright Year	2013
Description	Author affiliation: Dept. Electr. Eng., Univ. of California, Riverside, Riverside, CA, USA (Xue-Xin Liu; Palma-Rodriguez, A.A.; Rodriguez-Chavez, S.; Tan, S.X.-D.) \|\| Dept. of Comput. Sci. & Technol., Tsinghua Univ., Beijing, China (Yici Cai) \|\| Dept. of Electron., INAOE, Puebla, Mexico (Tlelo-Cuautle, E.)
Abstract	Yield estimation for analog integrated circuits are crucial for analog circuit design and optimization in the presence of process variations. In this paper, we present a novel analog yield estimation method based on performance bound analysis technique in frequency domain. The new method first derives the transfer functions of linear (or linearized) analog circuits via a graph-based symbolic analysis method. Then frequency response bounds of the transfer functions in terms of magnitude and phase are obtained by a nonlinear constrained optimization technique. To predict yield rate, bound information are employed to calculate Gaussian distribution functions. Experimental results show that the new method can achieve similar accuracy while delivers 20 times speedup over Monte Carlo simulation of HSPICE on some typical analog circuits.
Starting Page	761
Ending Page	766
File Size	4394219
Page Count	6
File Format	PDF
ISBN	9781467330299
ISSN	21536961
e-ISBN	9781467330305
DOI	10.1109/ASPDAC.2013.6509692
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2013-01-22
Publisher Place	Japan
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Transfer functions Monte Carlo methods Optimization Yield estimation Analog circuits Frequency-domain analysis Gain
Content Type	Text
Resource Type	Article

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1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
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3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
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