NDLI: Variability-aware memory management for nanoscale computing

Content Provider	IEEE Xplore Digital Library
Author	Dutt, N. Gupta, P. Nicolau, A. Bathen, L.A.D. Gottscho, M.
Copyright Year	2013
Description	Author affiliation: Dept. of Comput. Sci., Univ. of California, Irvine, Irvine, CA, USA (Dutt, N.; Nicolau, A.; Bathen, L.A.D.) \|\| Electr. Eng. Dept., Univ. of California, Los Angeles, Los Angeles, CA, USA (Gupta, P.; Gottscho, M.)
Abstract	As the semiconductor industry continues to push the limits of sub-micron technology, the ITRS expects hardware (e.g., die-to-die, wafer-to-wafer, and chip-to-chip) variations to continue increasing over the next few decades. As a result, it is imperative for designers to build variation-aware software stacks that may adapt and opportunistically exploit said variations to increase system performance/responsiveness as well as minimize power consumption. The memory subsystem is one of the largest components in today's computing system, a main contributor to the overall power consumption of the system, and therefore one of the most vulnerable components to the effects of variations (e.g., power). This paper discusses the concept of variability-aware memory management for nanoscale computing systems. We show how to opportunistically exploit the hardware variations in on-chip and off-chip memory at the system level through the deployment of variation-aware software stacks.
Starting Page	125
Ending Page	132
File Size	915842
Page Count	8
File Format	PDF
ISBN	9781467330299
ISSN	21536961
e-ISBN	9781467330305
DOI	10.1109/ASPDAC.2013.6509584
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2013-01-22
Publisher Place	Japan
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Hardware Memory management Software Random access memory Power demand System-on-chip Resource management
Content Type	Text
Resource Type	Article

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1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
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3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
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