NDLI: An efficient routing tree construction algorithm with buffer insertion, wire sizing and obstacle considerations

Content Provider	IEEE Xplore Digital Library
Author	Dechu, S. Shen, Z.C. Chu, C.C.N.
Copyright Year	2004
Description	Author affiliation: Phys. Design Autom. Group, Micron Technol. Inc., Boise, ID, USA (Dechu, S.)
Abstract	We propose a fast algorithm to construct a performance driven routing tree with simultaneous buffer insertion and wire sizing in the presence of wire and buffer obstacles. Several algorithms (J. Lillis et al., 1996; M. Hrkic et al., 2001, 2002; X. Tang et al., 2001) have been published addressing the routing tree construction problem. But all these algorithms are slow and not scalable. We propose an algorithm, which is fast and scalable with problem size. The main idea of our approach is to specify some important high-level features of the whole routing tree so that it can be broken down into several components. We apply stochastic search to find the best specification. Since we need very few high-level features, the size of stochastic search space is small which can be searched in very less time. The solutions for the components are either pregenerated and stored in lookup tables, or generated by extremely fast algorithms whenever needed. Since it is efficient to obtain solutions for components, it is also efficient to construct and evaluate the whole routing tree for each specification. Experimental results show that, for trees of moderate size, our algorithm is at least several hundred times faster than the recently proposed algorithms. Experimental results also show that the trees generated by our algorithm have almost same delay and resource consumption as the trees generated by SP-tree.
Sponsorship	IEEE Circuits and Syst. Soc. ACM SIGDA Inst. of Electron., Information and Commun. Eng. Information Processing Soc. of Japan
Starting Page	361
Ending Page	366
File Size	497812
Page Count	6
File Format	PDF
ISBN	0780381750
DOI	10.1109/ASPDAC.2004.1337600
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2004-01-27
Publisher Place	Japan
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Routing Wire Topology Integrated circuit interconnections Delay Design automation Stochastic processes Circuit optimization Modems Wiring
Content Type	Text
Resource Type	Article

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4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
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