NDLI: High-level area and power-up current estimation considering rich cell library

Content Provider	IEEE Xplore Digital Library
Author	Fei Li Lei He Basile, J.M. Patel, R.J. Ramamurthy, H.
Copyright Year	2004
Description	Author affiliation: University of California (Fei Li)
Abstract	Reducing the ever-growing leakage power is critical to power efficient designs. Leakage reduction techniques such as power-gating using sleep transistor insertion introduces large power-up current that may affect circuit reliability as well as introduce performance loss. We present an in-depth study of high-level power-up current modeling and estimation in the context of a full custom design environment with a rich cell library. We propose a methodology to estimate the circuit area in terms of gate count and maximum power-up current for any given logic function. We build novel estimation metrics based on logic synthesis and gate level analysis using only a small number of typical circuits, but no further logic synthesis and gate level analysis are needed during our estimation. Compared to time-consuming logic synthesis and gate level analysis, the average errors for circuits from a leading industrial design project are 23.59% for area and 21.44% for maximum power-up current. In contrast, estimation based on quick synthesis leads to llx area difference in gate count for an Bbit adder.
Sponsorship	IEEE Circuits and Syst. Soc. ACM SIGDA Inst. of Electron., Information and Commun. Eng. Information Processing Soc. of Japan
Starting Page	900
Ending Page	905
File Size	445905
Page Count	6
File Format	PDF
ISBN	0780381750
DOI	10.1109/ASPDAC.2004.1337723
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2004-01-27
Publisher Place	Japan
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Libraries Logic circuits Context modeling Logic gates Logic design Very large scale integration Helium Performance loss Circuit synthesis Error analysis
Content Type	Text
Resource Type	Article

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
6	Contents and Copyright Issues	Queries related to content curation and copyright issues	content@ndl.gov.in
7	National Digital Library of India Club (NDLI Club)	Queries related to NDLI Club formation, support, user awareness program, seminar/symposium, collaboration, social media, promotion, and outreach	clubsupport@ndl.gov.in
8	Digital Preservation Centre (DPC)	Assistance with digitizing and archiving copyright-free printed books	dpc@ndl.gov.in
9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in

High-level area and power-up current estimation considering rich cell library.

A worst-case circuit delay verification technique considering power grid voltage variations

FAST: A framework of accurate SER-estimation at transistor-level for logic circuits

Design error diagnosis and correction in VLSI digital circuits

Synthesis of high performance low power dynamic CMOS circuits

Extraction error diagnosis and correction in high-performance designs

Synthesis of full-adder circuit using reversible logic

Towards a more physical approach to gate modeling for timing, noise, and power

Probabilistic bottom-up RTL power estimation

High-level area and power-up current estimation considering rich cell library

Similar Documents

High-level area and power-up current estimation considering rich cell library.

A worst-case circuit delay verification technique considering power grid voltage variations

FAST: A framework of accurate SER-estimation at transistor-level for logic circuits

Design error diagnosis and correction in VLSI digital circuits

Synthesis of high performance low power dynamic CMOS circuits

Extraction error diagnosis and correction in high-performance designs

Synthesis of full-adder circuit using reversible logic

Towards a more physical approach to gate modeling for timing, noise, and power

Probabilistic bottom-up RTL power estimation

High-level area and power-up current estimation considering rich cell library