NDLI: Longest path selection for delay test under process variation

Content Provider	IEEE Xplore Digital Library
Author	Lu, X. Li, Z. Qiu, W. Walker, D.M.H. Shi, W.
Copyright Year	2004
Description	Author affiliation: Dept. of Electr. Eng., Texas A&M Univ., College Station, TX, USA (Lu, X.; Li, Z.)
Abstract	Under manufacturing process variation, a path through a fault site is called longest for delay test if there exists a process condition under which the path has the maximum delay among all paths through that fault site. There are often multiple longest paths for each fault site in the circuit, due to different process conditions. To detect the smallest delay fault, it is necessary to test all longest paths through the fault site. However, previous methods are either inefficient or their results include too many paths that are not longest. We present an efficient method to generate the longest path set for delay test under process variation. To capture both structural and systematic process correlation, we use linear delay functions to express path delays under process variation. A novel path-pruning technique is proposed to discard paths that are not longest, resulting in a significantly reduction in the number of paths compared with the previous best method. The new method can be applied to any process variation as long as its impact on delay is linear.
Sponsorship	IEEE Circuits and Syst. Soc. ACM SIGDA Inst. of Electron., Information and Commun. Eng. Information Processing Soc. of Japan
Starting Page	98
Ending Page	103
File Size	476466
Page Count	6
File Format	PDF
ISBN	0780381750
DOI	10.1109/ASPDAC.2004.1337547
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2004-01-27
Publisher Place	Japan
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Circuit faults Circuit testing Fault detection Electrical fault detection Performance evaluation Table lookup Manufacturing processes Delay lines Delay effects Propagation delay
Content Type	Text
Resource Type	Article

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
6	Contents and Copyright Issues	Queries related to content curation and copyright issues	content@ndl.gov.in
7	National Digital Library of India Club (NDLI Club)	Queries related to NDLI Club formation, support, user awareness program, seminar/symposium, collaboration, social media, promotion, and outreach	clubsupport@ndl.gov.in
8	Digital Preservation Centre (DPC)	Assistance with digitizing and archiving copyright-free printed books	dpc@ndl.gov.in
9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in

Longest-path selection for delay test under process variation

On effective criterion of path selection for delay testing

Tuple detection for path delay faults: a method for improving test set quality

A statistical fault coverage metric for realistic path delay faults

Path Selection for Transition Path Delay Faults

Generation of High Quality Non-Robust Tests for Path Delay Faults

Accelerated path delay fault simulation

Path delay test compaction with process variation tolerance

Classification and test generation for path-delay faults using single stuck-fault tests

Longest path selection for delay test under process variation

Similar Documents

Longest-path selection for delay test under process variation

On effective criterion of path selection for delay testing

Tuple detection for path delay faults: a method for improving test set quality

A statistical fault coverage metric for realistic path delay faults

Path Selection for Transition Path Delay Faults

Generation of High Quality Non-Robust Tests for Path Delay Faults

Accelerated path delay fault simulation

Path delay test compaction with process variation tolerance

Classification and test generation for path-delay faults using single stuck-fault tests

Longest path selection for delay test under process variation