NDLI: Large-scale linear circuit simulation with an inversed inductance matrix

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ASP-DAC 2004: Asia and South Pacific Design Automation Conference 2004 (IEEE Cat. No.04EX753)

ASP-DAC 2004: Asia and South Pacific Design Automation Conference 2004 (IEEE Cat. No.04EX753)

Proceedings of the ASP-DAC 2004 Asia and South Pacific Design Automation Conference 2004

ASP-DAC 2004 General Chair's Message

Techical Program Co-Chairs' Message

University LSI Design Contest

Keynote Address I - CITRIS: The Center for Information Technology Research in the Interest of Society at the University of California

Keynote address II - System level design technology for realizing an ambient intelligent environment

ASP-DAC 2003 Best Papers

ASP-DAC 2004 Best Papers

ASP-DAC Steering Committee

ASP-DAC 2004 Technical Program Committee

University LSI Design Contest Committee

List of reviewers

Table of contents

System level design technology for realizing an ambient intelligent environment

Fast, predictable and low energy memory references through architecture-aware compilation

Predictable design of low power systems by pre-implementation estimation and optimization

EuroSoC: towards a joint university/industry research infrastructure for system on chip and system in package

Abstraction and optimization of consistent floorplanning with pillar block constraints

Space-planning: placement of modules with controlled empty area by single-sequence

Layer assignment for reliable system-on-package

On handling arbitrary rectilinear shape constraint

Fixed-outline floorplanning through evolutionary search

Analog circuit behavioral modeling via wavelet collocation method with auto-companding

High-level modeling of continuous-time /spl Delta//spl Sigma/ A/D-converters using formal models

High-frequency noise in RF active CMOS mixers

On mismatch in the deep sub-micron era-from physics to circuits

Register binding and port assignment for multiplexer optimization

A thread partitioning algorithm in low power high-level synthesis

Minimization of fractional wordlength on fixed-point conversion for high-level synthesis

A procedure for obtaining a behavioral description for the control logic of a non-linear pipeline

TranGen: a SAT-based ATPG for path-oriented transition faults

Longest path selection for delay test under process variation

SRAM delay fault modeling and test algorithm development

An efficient design of non-linear CA based PRPG for VLSI circuit testing

Combinatorial group testing methods for the BIST diagnosis problem

Toward mobile phone Linux

Power control of CDMA systems with successive interference cancellation using the knowledge of battery power capacity

Rate analysis for streaming applications with on-chip buffer constraints

Performance-driven global placement via adaptive network characterization

Temperature-aware global placement

High speed layout synthesis for minimum-width CMOS logic cells via Boolean satisfiability

An integrated approach to timing-driven synthesis and placement of arithmetic circuits

Layer assignment for crosstalk risk minimization

CrtSmile: a CAD tool for CMOS RF transistor substrate modeling incorporating layout effects

NSGA-based parasitic-aware optimization of a 5GHz low-noise VCO

Analytical expressions for phase noise eigenfunctions of LC oscillators

Analysis of MOS cross-coupled LC-tank oscillators using short-channel device equations

Timing optimization by replacing flip-flops to latches

Enhancing the performance of multi-cycle path analysis in an industrial setting

An approach for reducing dynamic power consumption in synchronous sequential digital designs

Low power design using dual threshold voltage

Technology mapping and packing for coarse-grained, anti-fuse based FPGAs

Efficient RT-level fault diagnosis methodology

Design diagnosis using Boolean satisfiability

Testable design of GRM network with EXOR-tree for detecting stuck-at and bridging faults

Test data compression technique using selective don't-care identification

Re-configurable embedded core test protocol

Object-oriented modeling and synthesis of SystemC specifications

Application of UML for hardware design based on design process model

A cosynthesis algorithm for application specific processors with heterogeneous datapaths

Design methodology for SoC architectures based on reusable virtual cores

A mulitple level network approach for clock skew minimization with process variations

Layout techniques for on-chip interconnect inductance reduction

Piecewise quadratic waveform matching with successive chord iteration

Optimal design of high fan-in multiplexers via mixed-integer nonlinear programming

Adaptive supply voltage technique for low swing interconnects

A large-current-output boosted voltage generator with non-overlapping clock control for sub-1-V memory applications

Effects of noise and nonlinearity on the calibration of a non-binary capacitor array in a successive approximation analog-to-digital converter

Jitter spectral extraction for multi-gigahertz signal

A 35 dB-linear exponential function generator for VGA and AGC applications

A high efficiency 0.5W BTL class-D audio amplifier with RWDM technique

Efficient translation of Boolean formulas to CNF in formal verification of microprocessors

Using positive equality to prove liveness for pipelined microprocessors

On deriving equivalent architecture model from system specification

On compliance test of on-chip bus for SOC

Opportunities with the open architecture test system

New opportunities with the open architecture test system

Open architecture tester - What is a key issue of OAT?

Open architecture test system: not why but when!

New opportunities with the open architecture test system

"Signal integrity analysis in the open architecture"

Opportunities with the open architecture test system

Using C based logic synthesis to bridge the productivity gap

A place and route aware buffered Steiner tree construction

An efficient routing tree construction algorithm with buffer insertion, wire sizing and obstacle considerations

Modeling of coplanar waveguide for buffered clock tree

Decode filter cache for energy efficient instruction cache hierarchy in super scalar architectures

Mixed-clock issue queue design for energy aware, high-performance cores

Power-performance trade-off using pipeline delays

Exploiting program execution phases to trade power and performance for media workload

LPRAM: a low power DRAM with testability

Multiple specifications radio-frequency integrated circuit design with automatic template-driven layout retargeting

Hierarchical extraction and verification of symmetry constraints for analog layout automation

Multilevel placement with circuit schema based clustering in analog IC layouts

Model checking on state transition diagram

Efficient reachability checking using sequential SAT

Exploiting state encoding for invariant generation in induction-based property checking

Tradeoff routing resource, runtime and quality in buffered routing

Practical methodology of post-layout gate sizing for 15% more power saving

Interconnect design methods for memory design

Optimal planning for mesh-based power distribution

2.5D system integration: a design driven system implementation schema

An HMAC processor with integrated SHA-1 and MD5 algorithms

Design methodology for IRA codes

Embedded software generation from system level design languages

Fast and accurate timed execution of high level embedded software using HW/SW interface simulation model

Energy efficient code generation exploiting reduced bit-width instruction set architectures (rISA)

Memory access driven storage assignment for variables in embedded system design

MOSFET modeling for RF-CMOS design

RF design methodologies bridging system-IC-module design

Hierarchical random-walk algorithms for power grid analysis

A fast decoupling capacitor budgeting algorithm for robust on-chip power delivery

Large-scale linear circuit simulation with an inversed inductance matrix

DEPOGIT: dense power-ground interconnect architecture for physical design integrity

Design of real-time VGA 3-D image sensor using mixed-signal techniques

A bandwidth and memory efficient MPEG-4 shape encoder

A sub-mW MPEG-4 motion estimation processor core for mobile video application

Analog LSI for motion detection of approaching object with simple-shape recognition based on lower animal vision

350nm CMOS test-chip for architecture verification of real-time QVGA color-video segmentation at the 90nm technology node

A low-power graphics LSI integrating 29Mb embedded DRAM for mobile multimedia applications

A high efficiency 0.5W BTL class-D audio amplifier with RWDM technique

A small-area high-performance 512-point 2-dimensional FFT single-chip processor

Fast adaptive DC-DC conversion using dual-loop one-cycle control in standard digital CMOS process

A dual-band image-reject mixer for GPS with 64dB image rejection

Associative memory with fully parallel nearest-manhattan-distance search for low-power real-time single-chip applications

A performance comparison of PLLs for clock generation using ring oscillator VCO and LC oscillator in a digital CMOS process

A reliable low-power fast skew-compensation circuit

A retinal prosthetic device using a pulse-frequency-modulation CMOS image sensor

Compact 12-port multi-bank register file test-chip in 0.35/spl mu/m CMOS for highly parallel processors

A low power asynchronous java processor for contactless smart card

An image-sensor-based optical receiver fabricated in a standard 0.35-/spl mu/m CMOS technology for free-space optical communications

The flexible processor an approach for single-chip hardware emulation by dynamic reconfiguration

A V/sub DD/ and temperature independent CMOS voltage reference circuit

A dual-band switching digital controller for a buck converter

Golay and wavelet error control codes in VLSI

Timing measurement unit with multi-stage TVC for embedded memories

Development of a waveform sampling front-end ASIC for PET

A dynamic element matching circuit for multi-bit delta-sigma modulators

Design of POP-11 (PDP-11 on programmable chip)

A closed caption TV microcontroller

Improvement of saturation characteristics of a frequency-demodulation CMOS image sensor

Design and implementation of a secret key steganographic micro-architecture employing FPGA

Preserving synchronizing sequences of sequential circuits after retiming

A fast method to derive minimum SOPs for decomposable functions

Efficient computation of canonical form for boolean matching in large libraries

Disjoint-support boolean decomposition combining functional and structural methods

Transduction method for design of logic cell structure

The integration of vehicles into a ubiquitous computing environment computing and networking technologies for vehicles

Complexity analysis and speedup techniques for optimal buffer insertion with minimum cost

A buffer planning algorithm with congestion optimization

Buffer allocation algorithm with consideration of routing congestion

Integrating buffer planning with floorplanning for simultaneous multi-objective optimization

Verification of timed circuits with symbolic delays

Improved symbolic simulation by functional-space decomposition

Improving simulation-based verification by means of formal methods

Parallel verilog simulation: architecture and circuit partition

Minimizing energy consumption of multiple-processors-core systems with simultaneous task allocation, scheduling and voltage assignment

Dynamic voltage scaling of periodic and aperiodic tasks in priority-driven systems

Fast and efficient voltage scheduling by evolutionary slack distribution

Minimizing energy consumption of hard real-time systems with simultaneous tasks scheduling and voltage assignment using statistical data

A fast congestion estimator for routing with bounded detours

Accurate and eff icient flow based congestion estimation in floorplanning

A coupling and crosstalk considered timing-driven global routing algorithm for high performance circuit design

Liming-constrained congestion-driven global routing

Efficient octilinear steiner tree construction based on spanning graphs

Representative frequency for interconnect R(f)L(f)C extraction

A mixed-mode extraction flow for high performance microprocessors

An efficient method MEGCR for solving systems with multiple right-hand sides in 3-D parasitic inductance extraction

Fast and accurate extraction of 3-D interconnect resistance: improved quasi-multiple medium accelerated BEM method

Concept and extraction method of ESD-critical parameters for function-based layout-level ESD protection circuit design verification

Interconnect capacitance estimation for FPGAs

Area-minimal algorithm for LUT-based FPGA technology mapping with duplication-free restriction

Temporal floorplanning using 3D-subTCG

ReCSiP: a reconfigurable cell simulation platform: accelerating biological applications with FPGA

SmartGlue: an interface controller with auto reconfiguration for field programmable computing machine

An SoC architecture and its design methodology using unifunctional heterogeneous processor array

Instruction set and functional unit synthesis for SIMD processor cores

A high performance bus communication architecture through bus splitting

Automatic generation of bus functional models fromtransaction level models

A global bus power optimization methodology for physical design of memory dominated systems by coupling bus segmentation and activity driven block placement

Toward stochastic design for digital circuits - statistical static timing analysis

Physical CAD changes to incorporate design for lithography and manufacturability

Design-manufacturing interface for 0.13 um and below

Parametric reduced order modeling for interconnect analysis

Realizable parasitic reduction for distributed interconnects using matrix pencil technique

SPICE compatible circuit models for partial reluctance K

Frequency-dependent reluctance extraction

Future reconfigurable computing system

Enabling on-chip diversity through architectural communication design

Bandwidth tracing arbitration algorithm for mixed-clock SoC with dynamic priority adaptation

A novel memory size model for variable-mapping in system level design

A compressed frame buffer to reduce display power consumption in mobile systems

Instruction buffering exploration for low energy VLIWs with instruction clusters

A. static and dynamic energy reduction technique for I-cache and BTB in embedded processors

Resource-constrained low-power bus encoding with crosstalk delay elimination

Compiler based exploration of DSP energy savings by SIMD operations

Synthesizable HDL generation method for configurable VLIW processors

A non-iterative model for switching window computation with crosstalk noise

Gate delay calculation considering the crosstalk capacitances

A simplifiediyansmission-line based crosstalk noise model for on-chip RLC wiring

Minimization of the expected path length in BDDs based on local changes

Minimization of memory size for heterogeneous MDDs

Combining ordered best-first search with branch and bound for exact BDD minimization

Satisfiability and integer programming as complementary tools

ShatterPB: symmetry-breaking for pseudo-boolean formulas

Automatic process migration of datapath hard IP libraries

Priority assignment optimization for minimization of current surge in high performance power efficient clock-gated microprocessor

High-level area and power-up current estimation considering rich cell library

Call for papers /ASP-DAC 2005

Call for designs ASP-DAC 2005

Proceedings of the ASP-DAC Asia and South Pacific Design Automation Conference, 2003.

Proceedings of ASP-DAC/VLSI Design 2002. 7th Asia and South Pacific Design Automation Conference and 15h International Conference on VLSI Design

Proceedings of the ASP-DAC 2001. Asia and South Pacific Design Automation Conference 2001 (Cat. No.01EX455)

Proceedings 2000. Design Automation Conference. (IEEE Cat. No.00CH37106)

Proceedings of the ASP-DAC '99 Asia and South Pacific Design Automation Conference 1999 (Cat. No.99EX198)

Proceedings of 1998 Asia and South Pacific Design Automation Conference

Proceedings of ASP-DAC '97: Asia and South Pacific Design Automation Conference

Proceedings of ASP-DAC'95/CHDL'95/VLSI'95 with EDA Technofair

Large-scale linear circuit simulation with an inversed inductance matrix

Content Provider	IEEE Xplore Digital Library
Author	Mizuta, C. Iwai, J. Machida, K. Kage, T. Masuda, H.
Copyright Year	2004
Description	Author affiliation: Math. Syst. Inc., Tokyo, Japan (Mizuta, C.; Iwai, J.; Machida, K.)
Abstract	We show that by using an inversed form of an inductance matrix, the current variables become no more necessary in a transient analysis. Furthermore we have invented a way to remove them even in a steady state analysis while preserving the same sparse matrix topology throughout the both analyses. The removal has brought about a sufficiently effective speed-up and stability of calculation. It opens a way to the accurate numerical verification of large-scale signal integrity as in a power grid of LSI.
Sponsorship	IEEE Circuits and Syst. Soc. ACM SIGDA Inst. of Electron., Information and Commun. Eng. Information Processing Soc. of Japan
Starting Page	511
Ending Page	516
File Size	283588
Page Count	6
File Format	PDF
ISBN	0780381750
DOI	10.1109/ASPDAC.2004.1337628
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2004-01-27
Publisher Place	Japan
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Large-scale systems Linear circuits Circuit simulation Inductance Sparse matrices Transient analysis Steady-state Topology Power system stability Power grids
Content Type	Text
Resource Type	Article

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