NDLI: Area-minimal algorithm for LUT-based FPGA technology mapping with duplication-free restriction

Content Provider	IEEE Xplore Digital Library
Author	Chi-Chou Kao Yen-Tai Lai
Copyright Year	2004
Description	Author affiliation: National Pingtung Institute of Commerce (Chi-Chou Kao)
Abstract	Minimum area is one of the important objectives in technology mapping for lookup table-based FPGAs. It has been proven that the problem is NP-complete. This paper presents a polynomial time algorithm which can run in $O(n^{3})$ time to generate an efficient solution where n is the total number of gates in the circuit. The proposed algorithm partitions the graph representing the given circuit into subgraphs such that the solution can be obtained by merging the subgraph solutions. The greedy technique is then used to find the solution for each subgraph. It is shown that except for some cases the greedy method can find an optimal solution of a given problem. We have tested our algorithm on a set of benchmark examples. The experimental results demonstrate the effectiveness of our algorithm.
Sponsorship	IEEE Circuits and Syst. Soc. ACM SIGDA Inst. of Electron., Information and Commun. Eng. Information Processing Soc. of Japan
Starting Page	719
Ending Page	724
File Size	455754
Page Count	6
File Format	PDF
ISBN	0780381750
DOI	10.1109/ASPDAC.2004.1337687
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2004-01-27
Publisher Place	Japan
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Field programmable gate arrays Table lookup Partitioning algorithms Combinational circuits Polynomials Terminology Information technology Business Merging Circuit testing
Content Type	Text
Resource Type	Article

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1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
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