NDLI: A place and route aware buffered Steiner tree construction

Content Provider	IEEE Xplore Digital Library
Author	Sze, C.N. Hu, J. Alpert, C.J.
Copyright Year	2004
Description	Author affiliation: Dept. of Electr. Eng., Texas A&M Univ., College Station, TX, USA (Sze, C.N.; Hu, J.)
Abstract	In order to achieve timing closure on increasingly complex IC designs, buffer insertion needs to be performed on thousands of nets within an integrated physical synthesis system. In most of previous works, buffers may be inserted at any open space. Even when there may appear to be space for buffers in the alleys between large blocks, these regions are often densely packed or may be useful later to fix critical paths. In addition, a buffer solution may inadvertently force wires to go through routing congested regions. Therefore, within physical synthesis, a buffer insertion scheme needs to be aware of both placement congestion and routing congestion of the existing layout and so it has to be able to decide when to insert buffers in dense regions to achieve critical performance improvement and when to utilize the sparser regions of the chip. With the proposed Steiner tree adjustment technique, this work aims at finding congestion-aware buffered Steiner trees. Our tree adjustment technique takes a Steiner tree as input, modifies the tree and simultaneously handles the objectives of timing, placement and routing congestion. To our knowledge, this is the first study, which simultaneously considers these three objectives for the buffered Steiner tree problem. Experimental results confirm the effectiveness of our algorithm while it achieves up to 20x speed-up when comparing with the state-of-the-art algorithm (C.J. Alpert et al., 2003).
Sponsorship	IEEE Circuits and Syst. Soc. ACM SIGDA Inst. of Electron., Information and Commun. Eng. Information Processing Soc. of Japan
Starting Page	355
Ending Page	360
File Size	621292
Page Count	6
File Format	PDF
ISBN	0780381750
DOI	10.1109/ASPDAC.2004.1337599
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2004-01-27
Publisher Place	Japan
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Integrated circuit interconnections Topology Steiner trees Integrated circuit synthesis Wires Modems Circuit synthesis Timing Dynamic programming Polynomials
Content Type	Text
Resource Type	Article

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