NDLI: A performance-driven global routing algorithm with wire-sizing and buffer-insertion

Content Provider	IEEE Xplore Digital Library
Author	Deguchi, T. Koide, T. Wakabayashi, S.
Copyright Year	1998
Description	Author affiliation: Fac. of Eng., Hiroshima Univ., Japan (Deguchi, T.)
Abstract	This paper presents a timing-driven multi-layer global routing algorithm with wire-sizing and buffer-insertion. Wire-widening and buffer insertion allow us to reduce the path delay so that we can obtain a high-performance layout. In the proposed algorithm, first, a routing topology is determined with minimizing the delay of a net from the source of a net to each root of subtrees of the tree. Next the algorithm assigns nets to each layer under timing constraints and routes nets considering routability and performs wire-sizing and buffer-insertion to reduce the path delay. Then, HV-routing of nets is performed based on the routing trees obtained in the first phase, considering timing constraint. Finally, we verify the timing constraints and reroute nets based on the criticality of each net to determine which nets are suitable for wire-sizing and buffer-insertion. Experimental results show the effectiveness of our global routing method under timing constraints.
Starting Page	121
Ending Page	124
File Size	478247
Page Count	4
File Format	PDF
ISBN	0780351460
DOI	10.1109/APCCAS.1998.743673
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	1998-11-24
Publisher Place	Thailand
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Routing Delay Wire Timing Integrated circuit interconnections Wiring Topology High speed integrated circuits Logic circuits Very large scale integration
Content Type	Text
Resource Type	Article

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