NDLI: Performance-Driven Routing Tree Construction with Buffer Insertion, Wire Sizing under RLC Delay Model

Content Provider	IEEE Xplore Digital Library
Author	Chang Qi Gao-feng Wang Yue-hua Chen
Copyright Year	2007
Description	Author affiliation: Wuhan Univ., Wuhan (Chang Qi; Gao-feng Wang)
Abstract	In this paper, given a multi-terminal net, we propose a new approach to construct a performance-driven rectilinear Steiner tree with simultaneous buffer insertion and wiresizing optimization (PDRST/BW) under a higher order resistance-inductance-capacitance (RLC) delay model. This approach is based on the concept of sharing-buffer insertion and dynamic programming approach combined with a bottom-up rectilinear Steiner tree construction. The performances considered in this paper include the timing delay and the quality of signal waveform. Recently several algorithms have been published addressing the buffer insertion problem, but all these algorithms are not scalable and they can only handle the two-terminal nets or small size multi-terminal nets. Moreover, almost all these algorithms use the Elmore delay model. The experimental results show that our proposed approach is scalable and obtains better performance than those previous approaches for the test signal nets.
Starting Page	3418
Ending Page	3423
File Size	298670
Page Count	6
File Format	PDF
ISBN	9781424408276
DOI	10.1109/ICMA.2007.4304112
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2007-08-05
Publisher Place	China
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Routing Wire Propagation delay Timing Integrated circuit interconnections Dynamic programming Table lookup Libraries Signal design Very large scale integration RLC delay model performance-driven rectilinear Steiner tree buffer insertion wiresizing optimization
Content Type	Text
Resource Type	Article

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