NDLI: Leakage power estimation for deep submicron circuits in an ASIC design environment

Content Provider	IEEE Xplore Digital Library
Author	Kumar, R. Ravikumar, C.P.
Copyright Year	2002
Description	Author affiliation: Sasken Commun. Technol. Ltd., Bangalore, India (Kumar, R.)
Abstract	Static power dissipation due to leakage current in transistors constitutes an increasing fraction of the total power in modern semiconductor technologies. Current technology trends indicate that the leakage contribution will increase rapidly. Developing power efficient products will require consideration of static power in early phases of design development. Design houses that use RTL synthesis based flow for designing ASICs require a quick and reasonably accurate estimate of static power dissipation. This is important for making early packaging decisions and planning the power grid. Keeping this in view, we propose a simple model which enables estimation of static power early in the design phase. Our model is based on the experimental data obtained from simulations at the design level: ln P/sub leak//sup lib/=S/sup lib/ ln Cells+C/sup lib/, where S/sup lib/ and C/sup lib/ are the technology-dependent slope and intercept parameters of the model and "Cells" is the number of cells in the design. The model is validated for a large benchmark circuit and the leakage power predicted by our model is within 2% of the actual leakage power predicted by a popular tool used in the industry.
Sponsorship	VLSI Soc. India (VSI)
Starting Page	45
Ending Page	50
File Size	299285
Page Count	6
File Format	PDF
ISBN	0769514413
DOI	10.1109/ASPDAC.2002.994883
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2002-01-11
Publisher Place	India
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Application specific integrated circuits Power dissipation Threshold voltage Phase estimation Predictive models Very large scale integration Integrated circuit synthesis Communications technology Instruments Leakage current
Content Type	Text
Resource Type	Article

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4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
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