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| Content Provider | IEEE Xplore Digital Library |
|---|---|
| Author | Young, E.F.Y. Chu, C.C.N. Ho, M.L. |
| Copyright Year | 2002 |
| Description | Author affiliation: Dept. of Comput. Sci. & Eng., Univ. of Hong Kong, China (Young, E.F.Y.) |
| Abstract | In floorplan design, it is common that a designer will want to control the positions of some modules in final packing for various purposes such as data path alignment, I/O connection, etc.. There are several previous works (Young and Wong, 1998 and 1999; Young et al, 1999; Murata et al, 1997; Chang et al, 2000) focusing on a few particular kinds of placement constraint. In this paper, we present the first "unified method" to handle all of them simultaneously, including pre-placed constraint, range constraint, boundary constraint, alignment, abutment and clustering, etc., in general nonslicing floorplans. We have used incremental updates and an interesting reduced graphs idea to improve the runtime of the algorithm. We tested our method using some benchmark data with about one eighth of the modules having placement constraints and the results are very promising. Good packing with all the constraints satisfied can be obtained efficiently. |
| Sponsorship | VLSI Soc. India (VSI) |
| Starting Page | 661 |
| Ending Page | 667 |
| File Size | 346417 |
| Page Count | 7 |
| File Format | |
| ISBN | 0769514413 |
| DOI | 10.1109/ASPDAC.2002.995011 |
| Language | English |
| Publisher | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Publisher Date | 2002-01-11 |
| Publisher Place | India |
| Access Restriction | Subscribed |
| Rights Holder | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Subject Keyword | Data engineering Design engineering Computer science Runtime Clustering algorithms Circuit testing Benchmark testing Very large scale integration Design optimization Circuit optimization |
| Content Type | Text |
| Resource Type | Article |
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