NDLI: PREDICTMOS MOSFET model and its application to submicron CMOS inverter delay analysis

Content Provider	IEEE Xplore Digital Library
Author	Bhattacharyya, A.B. Ulman, S.
Copyright Year	2002
Description	Author affiliation: Dept. of Phys., Goa Univ., India (Bhattacharyya, A.B.)
Abstract	Predictive delay analysis is presented for a representative CMOS inverter with submicron device size using PREDICTMOS MOSFET model. As against SPICE, which adopts a time consuming numerical approach and relies more on empirical fitting of parameters for short channel devices, the predictive MOSFET model used is relatively simple and can be related to process and layout data with potential of estimation of the performance of a scaled design. The submicron CMOS inverter delay estimation under various loading and operative conditions have been compared against two benchmarks (a) Computer aided simulation with SPICE level 3 and (b) The analytical results of the Alpha Power Law based model. It is concluded that the PREDICTMOS model is potentially promising as a predictive analytic tool for submicron level design with transparency of device or circuit physics and an acceptable level of accuracy.
Sponsorship	VLSI Soc. India (VSI)
Starting Page	207
Ending Page	212
File Size	284098
Page Count	6
File Format	PDF
ISBN	0769514413
DOI	10.1109/ASPDAC.2002.994920
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2002-01-11
Publisher Place	India
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	MOSFET circuits Semiconductor device modeling Predictive models Inverters SPICE Delay estimation Computational modeling Analytical models Circuit simulation Computer simulation
Content Type	Text
Resource Type	Article

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4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
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