NDLI: Using Parallel Processing to Speed-Up Rotorcraft Air Vehicle Flight Test Analysis

Content Provider	IEEE Xplore Digital Library
Author	Carico, D. Chengjian He Lee, F. Lebron, S.
Copyright Year	2005
Description	Author affiliation: NAVAIR, Patuxent River, MD (Carico, D.)
Abstract	Rotorcraft air vehicle flight testing is required to determine how well the aircraft will perform in selected operational scenarios. The actual air vehicle flight test program may require extensive planning, instrumentation, flight testing, data analysis, and reporting. Considerable emphasis has been placed on working to reduce the cost and cycle time associated with conventional flight testing. One option with the potential to help reduce the cost and cycle time of air vehicle flight testing involves using credible simulation. Although numerous simulation models exist, very few have the capability to duplicate the flight test techniques taught at the US Navy Test Pilot School (USNTPS). With dedicated research and development, these classic flight test techniques have been implemented into a generic analytic model structure. The analytic model structure can be operated on a personal computer with a Linux operating system. The time required to run a complete analytic rotorcraft air vehicle flight test program can be overnight or much longer depending on the parameter variations selected for the specific computer run. A goal is to be able to use the analytic options to show how close the projected flight test matrix flight conditions approach flight limits. Another goal is to be able to show the sensitivity of selected flight test parameters while the test plan is being developed. A recent High Performance Computing (HPC) portfolio on Collaborative Simulation and Testing (CST) was established to help integrate analytic options to enhance flight testing. The CST-03 topic focuses on developing parallel processing options to greatly speed up the analytic ability to predict rotorcraft performance, stability, and control
Starting Page	1
Ending Page	8
File Size	630646
Page Count	8
File Format	PDF
ISBN	0780388704
DOI	10.1109/AERO.2005.1559591
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2005-03-05
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Parallel processing Vehicles Testing Aerospace simulation Costs Performance analysis Aircraft Aerospace electronics Performance evaluation Instruments
Content Type	Text
Resource Type	Article

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
6	Contents and Copyright Issues	Queries related to content curation and copyright issues	content@ndl.gov.in
7	National Digital Library of India Club (NDLI Club)	Queries related to NDLI Club formation, support, user awareness program, seminar/symposium, collaboration, social media, promotion, and outreach	clubsupport@ndl.gov.in
8	Digital Preservation Centre (DPC)	Assistance with digitizing and archiving copyright-free printed books	dpc@ndl.gov.in
9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in

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