NDLI: Single Event Effect Mitigation in ReConfigurable Computers for Space Applications

Content Provider	IEEE Xplore Digital Library
Author	Murray, P.L. VanBuren, D.
Copyright Year	2005
Description	Author affiliation: SEAKR Eng., Inc., Centennial, CO (Murray, P.L.; VanBuren, D.)
Abstract	Reconfigurable high performance on-board processing is a critical capability for many space systems. On board processing provides the ability to increase science data, provide real time decision making, and eliminates the latency associated with centralized downlinks and processing stations. Large SRAM based FPGAs provide a capable processing platform for these systems. Arrays of these devices can create systems providing 100's of GFLOP's of processing power. However, these devices have been shown to be susceptible to single event effects (SEE), and SEE mitigation techniques must be employed in order to reliably use them in space environments. Traditional methods such as triple modular redundancy (TMR) have been proven effective in mitigating SEE's, but with a tremendous price in terms of area, power, mass, and speed. Many applications can not accommodate the costs associated with a full TMR approach. However, TMR is only one method of SEU mitigation. This paper introduces a novel approach to SEE mitigation for high performance reconfigurable computer's (RCC). This approach eliminates the costs associated with full TMR SEE mitigation. The usage of this technique in processing systems increases the processing performance of a system by more than a factor of 2.5 over a full TMR only approach. For power, size, and mass sensitive space systems, this approach enables spacecrafts and missions that presently are not feasible
Starting Page	1
Ending Page	7
File Size	1282351
Page Count	7
File Format	PDF
ISBN	0780388704
DOI	10.1109/AERO.2005.1559551
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2005-03-05
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Computer applications Application software Costs Decision making Delay Downlink Random access memory Field programmable gate arrays Power system reliability Redundancy
Content Type	Text
Resource Type	Article

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1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
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