NDLI: Mitigation of Single-and Multiple-Cycle-Duration SETs using Double-Mode-Redundancy (DMR) in Time

Content Provider	IEEE Xplore Digital Library
Author	Kim, J.E. Lin, J. McMurchie, L. Sechen, C.
Copyright Year	2005
Description	Author affiliation: Dept. of Electr. Eng., Washington Univ., Seattle, WA (Kim, J.E.; Lin, J.; McMurchie, L.; Sechen, C.)
Abstract	TMR-in-hardware is a traditional architectural solution to radiation hardening. Simple in concept, TMR-in-hardware incurs at least 3times power and area penalties over the unhardened singlet computation. In this paper we focus upon compute-intensive pipelined computations and present an efficient alternative - dual mode redundancy (DMR). DMR-in-time utilizes dual computation threads to detect an error. To correct an error DMR-in-time utilizes relatively small input and output queues for rolling back the computation to a known correct state. DMR-in-time incurs only a 2times decrease in throughput, requires no downtime for error correction, and has power requirements only marginally greater than the unhardened singlet computation
Starting Page	1
Ending Page	10
File Size	399966
Page Count	10
File Format	PDF
ISBN	0780388704
DOI	10.1109/AERO.2005.1559556
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2005-03-05
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Registers Hardware Error correction Clocks Delay Power engineering computing Throughput Logic Yarn Single event transient
Content Type	Text
Resource Type	Article

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Mitigation of Single-and Multiple-Cycle-Duration SETs using Double-Mode-Redundancy (DMR) in Time