NDLI: Space based radar on-board processing architecture

Content Provider	IEEE Xplore Digital Library
Author	Vaillancourt, S.
Copyright Year	2005
Description	Author affiliation: SEAKR Eng., Inc., Centennial, CO (Vaillancourt, S.)
Abstract	This paper describes system-level issues and solutions for space-based radar on-board processing. A modular, upgradeable architecture has been defined and SEAKR Engineering has built three module types as a risk-reduction effort. The memory modules are scalable to 128 Gbits/board with 16 Gbps of I/O capacity. The processing element boards are FPGA-based and use five Xilinx Virtex-II Pro-70 parts. Four FPGAs each have four banks of 18Mbit fast SRAM and the fifth FPGA has 512 MBytes of SDRAM. There are 10 Gbps interconnects between the FPGAs and two 8Gbps external I/O ports. The network switch module is based on RapidIO with the first version handling 4 bidirectional ports with 8Gbps full duplex per port. System partitioning and thermal issues have led to the use of heat pipes for hot parts and advanced materials for the chassis. The system power supply has also been considered to provide 1000 Watts from the system bus to the high-current, low voltages used by the advanced deep sub-micron parts
Starting Page	2190
Ending Page	2195
File Size	2231374
Page Count	6
File Format	PDF
ISBN	0780388704
DOI	10.1109/AERO.2005.1559511
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2005-03-05
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Spaceborne radar Switches Synthetic aperture radar Bandwidth Delay Computer architecture Power system reliability Low earth orbit satellites Sensor arrays Field programmable gate arrays
Content Type	Text
Resource Type	Article

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