NDLI: COMP: Compiler Optimizations for Manycore Processors

Please wait, while we are loading the content...

CAMEO: A Two-Level Memory Organization with Capacity of Main Memory and Flexibility of Hardware-Managed Cache

Locality-Aware Mapping of Nested Parallel Patterns on GPUs

Load Value Approximation

Iso-X: A Flexible Architecture for Hardware-Managed Isolated Execution

RpStacks: Fast and Accurate Processor Design Space Exploration Using Representative Stall-Event Stacks

Calculating Architectural Vulnerability Factors for Spatial Multi-bit Transient Faults

Skewed Compressed Caches

Voltage Noise in Multi-Core Processors: Empirical Characterization and Optimization Opportunities

SMiTe: Precise QoS Prediction on Real-System SMT Processors to Improve Utilization in Warehouse Scale Computers

NoC Architectures for Silicon Interposer Systems: Why Pay for more Wires when you Can Get them (from your interposer) for Free?

Wormhole: Wisely Predicting Multidimensional Branches

Protean Code: Achieving Near-Free Online Code Transformations for Warehouse Scale Computers

DaDianNao: A Machine-Learning Supercomputer

Transparent Hardware Management of Stacked DRAM as Part of Memory

Accelerating Irregular Algorithms on GPGPUs Using Fine-Grain Hardware Worklists

Arbitrary Modulus Indexing

Random Fill Cache Architecture

GPUMech: GPU Performance Modeling Technique Based on Interval Analysis

Using ECC Feedback to Guide Voltage Speculation in Low-Voltage Processors

Adaptive Cache Management for Energy-Efficient GPU Computing

Enabling Realistic Fine-Grain Voltage Scaling with Reconfigurable Power Distribution Networks

A Front-end Execution Architecture for High Energy Efficiency

Hi-Rise: A High-Radix Switch for 3D Integration with Single-cycle Arbitration

Bias-Free Branch Predictor

Compiler Support for Optimizing Memory Bank-Level Parallelism

B-Fetch: Branch Prediction Directed Prefetching for Chip-Multiprocessors

Unison Cache: A Scalable and Effective Die-Stacked DRAM Cache

PORPLE: An Extensible Optimizer for Portable Data Placement on GPU

FIRM: Fair and High-Performance Memory Control for Persistent Memory Systems

CC-Hunter: Uncovering Covert Timing Channels on Shared Processor Hardware

PyMTL: A Unified Framework for Vertically Integrated Computer Architecture Research

Harnessing Soft Computations for Low-Budget Fault Tolerance

Futility Scaling: High-Associativity Cache Partitioning

Micro-Sliced Virtual Processors to Hide the Effect of Discontinuous CPU Availability for Consolidated Systems

Execution Drafting: Energy Efficiency Through Computation Deduplication

Multi-GPU System Design with Memory Networks

Loop-Aware Memory Prefetching Using Code Block Working Sets

Architectural Specialization for Inter-Iteration Loop Dependence Patterns

PipeCheck: Specifying and Verifying Microarchitectural Enforcement of Memory Consistency Models

Bi-Modal DRAM Cache: A Scalable and Effective Die-Stacked DRAM Cache

Exploring the Design Space of SPMD Divergence Management on Data-Parallel Architectures

Short-Circuiting Memory Traffic in Handheld Platforms

Continuous, Low Overhead, Run-Time Validation of Program Executions

PPEP: Online Performance, Power, and Energy Prediction Framework and DVFS Space Exploration

Dodec: Random-Link, Low-Radix On-Chip Networks

BuMP: Bulk Memory Access Prediction and Streaming

Specializing Compiler Optimizations through Programmable Composition for Dense Matrix Computations

Equalizer: Dynamic Tuning of GPU Resources for Efficient Execution

Citadel: Efficiently Protecting Stacked Memory from Large Granularity Failures

Managing GPU Concurrency in Heterogeneous Architectures

Efficient Memory Virtualization: Reducing Dimensionality of Nested Page Walks

A Practical Methodology for Measuring the Side-Channel Signal Available to the Attacker for Instruction-Level Events

COMP: Compiler Optimizations for Manycore Processors

COMP: Compiler Optimizations for Manycore Processors

Content Provider	ACM Digital Library
Author	Yang, Yi Chakradhar, Srimat Song, Linhai Feng, Min Ravi, Nishkam
Abstract	Applications executing on multicore processors can now easily offload computations to manycore processors, such as Intel Xeon Phi coprocessors. However, it requires high levels of expertise and effort to tune such offloaded applications to realize high-performance execution. Previous efforts have focused on optimizing the execution of offloaded computations on manycore processors. However, we observe that the data transfer overhead between multicore and manycore processors, and the limited device memories of manycore processors often constrain the performance gains that are possible by offloading computations. In this paper, we present three source-to-source compiler optimizations that can significantly improve the performance of applications that offload computations to manycore processors. The first optimization automatically transforms offloaded codes to enable data streaming, which overlaps data transfer between multicore and manycore processors with computations on these processors to hide data transfer overhead. This optimization is also designed to minimize the memory usage on manycore processors, while achieving the optimal performance. The second compiler optimization re-orders computations to regularize irregular memory accesses. It enables data streaming and factorization on manycore processors, even when the memory access patterns in the original source codes are irregular. Finally, our new shared memory mechanism provides efficient support for transferring large pointer-based data structures between hosts and manycore processors. Our evaluation shows that the proposed compiler optimizations benefit 9 out of 12 benchmarks. Compared with simply offloading the original parallel implementations of these benchmarks, we can achieve 1.16x-52.21x speedups.
Starting Page	659
Ending Page	671
Page Count	13
File Format	PDF
ISBN	9781479969982
ISSN	10724451
DOI	10.1109/MICRO.2014.30
Language	English
Publisher	Association for Computing Machinery (ACM)
Publisher Date	2014-12-13
Access Restriction	Subscribed
Content Type	Text
Resource Type	Article

Central Library (ISO-9001:2015 Certified)
Indian Institute of Technology Kharagpur
Kharagpur, West Bengal, India | PIN - 721302

See location in the Map
03222 282435
Mail: support@ndl.gov.in

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
6	Contents and Copyright Issues	Queries related to content curation and copyright issues	content@ndl.gov.in
7	National Digital Library of India Club (NDLI Club)	Queries related to NDLI Club formation, support, user awareness program, seminar/symposium, collaboration, social media, promotion, and outreach	clubsupport@ndl.gov.in
8	Digital Preservation Centre (DPC)	Assistance with digitizing and archiving copyright-free printed books	dpc@ndl.gov.in
9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in