NDLI: B-Fetch: Branch Prediction Directed Prefetching for Chip-Multiprocessors

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B-Fetch: Branch Prediction Directed Prefetching for Chip-Multiprocessors

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B-Fetch: Branch Prediction Directed Prefetching for Chip-Multiprocessors

Content Provider	ACM Digital Library
Author	Gratz, Paul Sharma, Prabal Kim, Jinchun Panda, Reena Jimenez, Daniel Kadjo, David
Abstract	For decades, the primary tools in alleviating the "Memory Wall" have been large cache hierarchies and data prefetchers. Both approaches, become more challenging in modern, Chip-multiprocessor (CMP) design. Increasing the last-level cache (LLC) size yields diminishing returns in terms of performance per Watt; given VLSI power scaling trends, this approach becomes hard to justify. These trends also impact hardware budgets for prefetchers. Moreover, in the context of CMPs running multiple concurrent processes, prefetching accuracy is critical to prevent cache pollution effects. These concerns point to the need for a light-weight prefetcher with high accuracy. Existing data prefetchers may generally be classified as low-overhead and low accuracy (Next-n, Stride, etc.) or high-overhead and high accuracy (STeMS, ISB). We propose B-Fetch: a data prefetcher driven by branch prediction and effective address value speculation. B-Fetch leverages control flow prediction to generate an expected future path of the executing application. It then speculatively computes the effective address of the load instructions along that path based upon a history of past register transformations. Detailed simulation using a cycle accurate simulator shows a geometric mean speedup of 23.4% for single-threaded workloads, improving to 28.6% for multi-application workloads over a baseline system without prefetching. We find that B-Fetch outperforms an existing "best-of-class" light-weight prefetcher under single-threaded and multi programmed workloads by 9% on average, with 65% less storage overhead.
Starting Page	623
Ending Page	634
Page Count	12
File Format	PDF
ISBN	9781479969982
ISSN	10724451
DOI	10.1109/MICRO.2014.29
Language	English
Publisher	Association for Computing Machinery (ACM)
Publisher Date	2014-12-13
Access Restriction	Subscribed
Subject Keyword	Bfetch Prefetching Branch prediction Data cache Chip-multiprocessors
Content Type	Text
Resource Type	Article

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B-Fetch: Branch Prediction Directed Prefetching for Chip-Multiprocessors

B-Fetch: Branch Prediction Directed Prefetching for In-Order Processors

Fetch directed instruction prefetching (1999).

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In Proceedings of the 32nd Annual International Symposium on Microarchitecture (MICRO-32), November 1999. (1999)

Adaptive prefetching for shared cache based chip multiprocessors

Instruction cache prefetching directed by branch prediction

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B-Fetch: Branch Prediction Directed Prefetching for Chip-Multiprocessors

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