NDLI: Bi-Modal DRAM Cache: A Scalable and Effective Die-Stacked DRAM Cache

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Bi-Modal DRAM Cache: A Scalable and Effective Die-Stacked DRAM Cache

Content Provider	ACM Digital Library
Author	Gulur, Nagendra Govindarajan, R. Manikantan, R. Mehendale, Mahesh
Abstract	In this paper, we present Bi-Modal Cache - a flexible stacked DRAM cache organization which simultaneously achieves several objectives: (i) improved cache hit ratio, (ii) moving the tag storage overhead to DRAM, (iii) lower cache hit latency than tags-in-SRAM, and (iv) reduction in off-chip bandwidth wastage. The Bi-Modal Cache addresses the miss rate versus off-chip bandwidth dilemma by organizing the data in a bi-modal fashion - blocks with high spatial locality are organized as large blocks and those with little spatial locality as small blocks. By adaptively selecting the right granularity of storage for individual blocks at run-time, the proposed DRAM cache organization is able to make judicious use of the available DRAM cache capacity as well as reduce the off-chip memory bandwidth consumption. The Bi-Modal Cache improves cache hit latency despite moving the metadata to DRAM by means of a small SRAM based Way Locator. Further by leveraging the tremendous internal bandwidth and capacity that stacked DRAM organizations provide, the Bi-Modal Cache enables efficient concurrent accesses to tags and data to reduce hit time. Through detailed simulations, we demonstrate that the Bi-Modal Cache achieves overall performance improvement (in terms of Average Normalized Turnaround Time (ANTT)) of 10.8%, 13.8% and 14.0% in 4-core, 8-core and 16-core workloads respectively.
Starting Page	38
Ending Page	50
Page Count	13
File Format	PDF
ISBN	9781479969982
ISSN	10724451
DOI	10.1109/MICRO.2014.36
Language	English
Publisher	Association for Computing Machinery (ACM)
Publisher Date	2014-12-13
Access Restriction	Subscribed
Content Type	Text
Resource Type	Article

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