NDLI: Protean Code: Achieving Near-Free Online Code Transformations for Warehouse Scale Computers

Please wait, while we are loading the content...

CAMEO: A Two-Level Memory Organization with Capacity of Main Memory and Flexibility of Hardware-Managed Cache

Locality-Aware Mapping of Nested Parallel Patterns on GPUs

Load Value Approximation

Iso-X: A Flexible Architecture for Hardware-Managed Isolated Execution

RpStacks: Fast and Accurate Processor Design Space Exploration Using Representative Stall-Event Stacks

Calculating Architectural Vulnerability Factors for Spatial Multi-bit Transient Faults

Skewed Compressed Caches

Voltage Noise in Multi-Core Processors: Empirical Characterization and Optimization Opportunities

SMiTe: Precise QoS Prediction on Real-System SMT Processors to Improve Utilization in Warehouse Scale Computers

NoC Architectures for Silicon Interposer Systems: Why Pay for more Wires when you Can Get them (from your interposer) for Free?

Wormhole: Wisely Predicting Multidimensional Branches

Protean Code: Achieving Near-Free Online Code Transformations for Warehouse Scale Computers

DaDianNao: A Machine-Learning Supercomputer

Transparent Hardware Management of Stacked DRAM as Part of Memory

Accelerating Irregular Algorithms on GPGPUs Using Fine-Grain Hardware Worklists

Arbitrary Modulus Indexing

Random Fill Cache Architecture

GPUMech: GPU Performance Modeling Technique Based on Interval Analysis

Using ECC Feedback to Guide Voltage Speculation in Low-Voltage Processors

Adaptive Cache Management for Energy-Efficient GPU Computing

Enabling Realistic Fine-Grain Voltage Scaling with Reconfigurable Power Distribution Networks

A Front-end Execution Architecture for High Energy Efficiency

Hi-Rise: A High-Radix Switch for 3D Integration with Single-cycle Arbitration

Bias-Free Branch Predictor

Compiler Support for Optimizing Memory Bank-Level Parallelism

B-Fetch: Branch Prediction Directed Prefetching for Chip-Multiprocessors

Unison Cache: A Scalable and Effective Die-Stacked DRAM Cache

PORPLE: An Extensible Optimizer for Portable Data Placement on GPU

FIRM: Fair and High-Performance Memory Control for Persistent Memory Systems

CC-Hunter: Uncovering Covert Timing Channels on Shared Processor Hardware

PyMTL: A Unified Framework for Vertically Integrated Computer Architecture Research

Harnessing Soft Computations for Low-Budget Fault Tolerance

Futility Scaling: High-Associativity Cache Partitioning

Micro-Sliced Virtual Processors to Hide the Effect of Discontinuous CPU Availability for Consolidated Systems

Execution Drafting: Energy Efficiency Through Computation Deduplication

Multi-GPU System Design with Memory Networks

Loop-Aware Memory Prefetching Using Code Block Working Sets

Architectural Specialization for Inter-Iteration Loop Dependence Patterns

PipeCheck: Specifying and Verifying Microarchitectural Enforcement of Memory Consistency Models

Bi-Modal DRAM Cache: A Scalable and Effective Die-Stacked DRAM Cache

Exploring the Design Space of SPMD Divergence Management on Data-Parallel Architectures

Short-Circuiting Memory Traffic in Handheld Platforms

Continuous, Low Overhead, Run-Time Validation of Program Executions

PPEP: Online Performance, Power, and Energy Prediction Framework and DVFS Space Exploration

Dodec: Random-Link, Low-Radix On-Chip Networks

BuMP: Bulk Memory Access Prediction and Streaming

Specializing Compiler Optimizations through Programmable Composition for Dense Matrix Computations

Equalizer: Dynamic Tuning of GPU Resources for Efficient Execution

Citadel: Efficiently Protecting Stacked Memory from Large Granularity Failures

Managing GPU Concurrency in Heterogeneous Architectures

Efficient Memory Virtualization: Reducing Dimensionality of Nested Page Walks

A Practical Methodology for Measuring the Side-Channel Signal Available to the Attacker for Instruction-Level Events

COMP: Compiler Optimizations for Manycore Processors

Protean Code: Achieving Near-Free Online Code Transformations for Warehouse Scale Computers

Content Provider	ACM Digital Library
Author	Mars, Jason Zhang, Yunqi Tang, Lingjia Laurenzano, Michael A.
Abstract	Rampant dynamism due to load fluctuations, co-runner changes, and varying levels of interference poses a threat to application quality of service (QoS) and has limited our ability to allow co-locations in modern warehouse scale computers (WSCs). Instruction set features such as the non-temporal memory access hints found in modern ISAs (both ARM and x86) may be useful in mitigating these effects. However, despite the challenge of this dynamism and the availability of an instruction set mechanism that might help address the problem, a key capability missing in the system software stack in modern WSCs is the ability to dynamically transform (and re-transform) the executing application code to apply these instruction set features when necessary. In this work we introduce protean code, a novel approach for enacting arbitrary compiler transformations at runtime for native programs running on commodity hardware with negligible (<1%) overhead. The fundamental insight behind the underlying mechanism of protean code is that, instead of maintaining full control throughout the program's execution as with traditional dynamic optimizers, protean code allows the original binary to execute continuously and diverts control flow only at a set of virtualized points, allowing rapid and seamless rerouting to the new code variants. In addition, the protean code compiler embeds IR with high-level semantic information into the program, empowering the dynamic compiler to perform rich analysis and transformations online with little overhead. Using a fully functional protean code compiler and runtime built on LLVM, we design PC3D, Protean Code for Cache Contention in Datacenters. PC3D dynamically employs non-temporal access hints to achieve utilization improvements of up to 2.8x (1.5x on average) higher than state-of-the-art contention mitigation runtime techniques at a QoS target of 98%.
Starting Page	558
Ending Page	570
Page Count	13
File Format	PDF
ISBN	9781479969982
ISSN	10724451
DOI	10.1109/MICRO.2014.21
Language	English
Publisher	Association for Computing Machinery (ACM)
Publisher Date	2014-12-13
Access Restriction	Subscribed
Subject Keyword	Compiler Datacenter Warehouse scale computer Resource sharing Optimization Cache Dynamic compiler
Content Type	Text
Resource Type	Article

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
6	Contents and Copyright Issues	Queries related to content curation and copyright issues	content@ndl.gov.in
7	National Digital Library of India Club (NDLI Club)	Queries related to NDLI Club formation, support, user awareness program, seminar/symposium, collaboration, social media, promotion, and outreach	clubsupport@ndl.gov.in
8	Digital Preservation Centre (DPC)	Assistance with digitizing and archiving copyright-free printed books	dpc@ndl.gov.in
9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in

Protean Code: Achieving Near-Free Online Code Transformations for Warehouse Scale Computers

Protean Code: Achieving Near-free Online Code Transformations for Warehouse Scale Computers

ReQoS: reactive static/dynamic compilation for QoS in warehouse scale computers

ReQoS:reactive static/dynamic compilation for QoS in warehouse scale computers (SIGP, Vol. 48, Issue. 4)

ReQoS:reactive static/dynamic compilation for QoS in warehouse scale computers (CARN, Vol. 41, Issue. 1)

Heterogeneous energy-efficient cache design in warehouse scale computers

SMiTe: Precise QoS Prediction on Real-System SMT Processors to Improve Utilization in Warehouse Scale Computers

Making STMs Cache Friendly with Compiler Transformations

MEMSCOPT: A source-to-source compiler for dynamic code analysis and loop transformations

Protean Code: Achieving Near-Free Online Code Transformations for Warehouse Scale Computers

Similar Documents

Protean Code: Achieving Near-Free Online Code Transformations for Warehouse Scale Computers

Protean Code: Achieving Near-free Online Code Transformations for Warehouse Scale Computers

ReQoS: reactive static/dynamic compilation for QoS in warehouse scale computers

ReQoS:reactive static/dynamic compilation for QoS in warehouse scale computers (SIGP, Vol. 48, Issue. 4)

ReQoS:reactive static/dynamic compilation for QoS in warehouse scale computers (CARN, Vol. 41, Issue. 1)

Heterogeneous energy-efficient cache design in warehouse scale computers

SMiTe: Precise QoS Prediction on Real-System SMT Processors to Improve Utilization in Warehouse Scale Computers

Making STMs Cache Friendly with Compiler Transformations

MEMSCOPT: A source-to-source compiler for dynamic code analysis and loop transformations

Protean Code: Achieving Near-Free Online Code Transformations for Warehouse Scale Computers