NDLI: A fault tolerant, area efficient architecture for Shor's factoring algorithm

Content Provider	ACM Digital Library
Author	Isailovic, Nemanja Patel, Yatish Whitney, Mark G. Kubiatowicz, John
Abstract	We optimize the area and latency of Shor's factoring while simultaneously improving fault tolerance through: (1) balancing the use of ancilla generators, (2) aggressive optimization of error correction, and (3) tuning the core adder circuits. Our custom CAD flow produces detailed layouts of the physical components and utilizes simulation to analyze circuits in terms of area, latency, and success probability. We introduce a metric, called ADCR, which is the probabilistic equivalent of the classic Area-Delay product. Our error correction optimization can reduce ADCR by order of magnitude or more. Contrary to conventional wisdom, we show that the area of an optimized quantum circuit is not dominated exclusively by error correction. Further, our adder evaluation shows that quantum carry-lookahead adders (QCLA) beat ripple-carry adders in ADCR, despite being larger and more complex. We conclude with what we believe is one of most accurate estimates of the area and latency required for 1024-bit Shor's factorization: 7659 $mm^{2}$ for the smallest circuit and 6 x $10^{8}$ seconds for the fastest circuit.
Starting Page	383
Ending Page	394
Page Count	12
File Format	PDF
ISSN	01635964
DOI	10.1145/1555815.1555802
Journal	ACM SIGARCH Computer Architecture News (CARN)
Volume Number	37
Issue Number	3
Language	English
Publisher	Association for Computing Machinery (ACM)
Publisher Date	1981-04-01
Publisher Place	New York
Access Restriction	One Nation One Subscription (ONOS)
Subject Keyword	Control Ion trap Quantum computing Layout Cad
Content Type	Text
Resource Type	Article

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4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
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