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| Content Provider | ACM Digital Library |
|---|---|
| Author | Roth, Amir Hilton, Andrew |
| Abstract | CPR/CFP (Checkpoint Processing and Recovery/Continual Flow Pipeline) support an adaptive instruction window that scales to tolerate last-level cache misses. CPR/CFP scale the register file by aggressively reclaiming the destination registers of many in-flight instructions. However, an analogous mechanism does not exist for stores and loads. As the window expands, CPR/CFP processors must track all in-flight stores and loads to support forwarding and detect memory ordering violations. The previously-described SVW (Store Vulnerability Window) and SQIP (Store Queue Index Prediction) schemes provide scalable, non-associative load and store queues, respectively. However, they don't work smoothly in a CPR/CFP context. SVW/SQIP rely on the ability to dynamically stall some loads until a specific older store writes to the cache. Enforcing this serialization in CPR/CFP is expensive if the load and store are in the same checkpoint. We introduce two complementary procedures that implement this serialization efficiently. Decoupled Store Completion (DSC) allows stores to write to the cache before the enclosing checkpoint completes execution. Silent Deterministic Replay (SDR) supports mis-speculation recovery in the presence of DSC by replaying loads older than completed stores using values from the load queue. The combination of DSC and SDR enables an SVW/SQIP based CPR/CFP memory system that outperforms previous designs while occupying less area. |
| Starting Page | 245 |
| Ending Page | 254 |
| Page Count | 10 |
| File Format | |
| ISSN | 01635964 |
| DOI | 10.1145/1555815.1555786 |
| Journal | ACM SIGARCH Computer Architecture News (CARN) |
| Volume Number | 37 |
| Issue Number | 3 |
| Language | English |
| Publisher | Association for Computing Machinery (ACM) |
| Publisher Date | 1981-04-01 |
| Publisher Place | New York |
| Access Restriction | One Nation One Subscription (ONOS) |
| Subject Keyword | Load-store queues Checkpoint processors |
| Content Type | Text |
| Resource Type | Article |
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