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| Content Provider | ACM Digital Library |
|---|---|
| Author | Bernat, Guillem QuiƱones, Eduardo Paolieri, Marco Cazorla, Francisco J. Valero, Mateo |
| Abstract | The increasing demand for new functionalities in current and future hard real-time embedded systems like automotive, avionics and space industries is driving an increase in the performance required in embedded processors. Multicore processors represent a good design solution for such systems due to their high performance, low cost and power consumption characteristics. However, hard real-time embedded systems require time analyzability and current multicore processors are less analyzable than single-core processors due to the interferences between different tasks when accessing shared hardware resources. In this paper we propose a multicore architecture with shared resources that allows the execution of applications with hard real-time and non hard real-time constraints at the same time, providing time analizability for the hard real-time tasks so that they can meet their deadlines. Moreover our architecture proposal provides high-performance for the non hard real-time tasks. |
| Starting Page | 57 |
| Ending Page | 68 |
| Page Count | 12 |
| File Format | |
| ISSN | 01635964 |
| DOI | 10.1145/1555815.1555764 |
| Journal | ACM SIGARCH Computer Architecture News (CARN) |
| Volume Number | 37 |
| Issue Number | 3 |
| Language | English |
| Publisher | Association for Computing Machinery (ACM) |
| Publisher Date | 1981-04-01 |
| Publisher Place | New York |
| Access Restriction | One Nation One Subscription (ONOS) |
| Subject Keyword | Interconnection network Multicore Wcet Analyzability Hard real-time Cache partitioning Real-time embedded systems |
| Content Type | Text |
| Resource Type | Article |
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