NDLI: Low-power and area efficient binary coded decimal adder design using a look up table-based field programmable gate array

Content Provider	IET Digital Library
Author	Sworna, Zarrin Tasnim Haque, Mubin Ul Tara, Nazma Babu, Hafiz Md. Hasan Biswas, Ashis Kumar
Abstract	The binary coded decimal (BCD) system is suitable for digital communication, which can be designed by field programmable gate array (FPGA) technology, where look up table (LUT) is one of the major components of FPGA. In this study, the authors proposed a low power and area efficient LUT-based BCD adder which is constructed basically in three steps: First, a new technique is introduced for the BCD addition to obtain the correct BCD digit. Second, a new controller circuit of LUT is presented which is designed to select and send Read/Write voltage to memory cell for performing Read or Write operation. Finally, a compact BCD adder is designed using the proposed LUT. Their proposed 2-input LUT outperforms the existing best one providing 65.8% improvement in terms of area, 44.1% for Read operation and 43.5% for Write operation in power consumption. The proposed BCD adder using FPGA gains a radical achievement compared with the existing best-known LUT-based BCD adder providing prominent better performance of 65.6% in area and 48.3% less power consumption.
Starting Page	163
Ending Page	172
Page Count	10
ISSN	1751858X
Volume Number	10
e-ISSN	17518598
Issue Number	Issue 3, May (2016)
Alternate Webpage(s)	https://digital-library.theiet.org/content/journals/iet-cds/10/3
Alternate Webpage(s)	https://digital-library.theiet.org/content/journals/10.1049/iet-cds.2015.0213
Journal	IET Circuits, Devices & Systems
Publisher Date	2016-05-01
Access Restriction	Open
Rights Holder	© The Institution of Engineering and Technology
Subject Keyword	2-input LUT Adder BCD Addition BCD Digit Binary Codes Code Compact BCD Adder Controller Circuit Electrical/electronic Equipment Energy Utilisation Field Programmable Gate Array FPGA Logic And Switching Circuit Logic Circuit Look Up Table Low Power Electronics Low-power Area Efficient Binary Coded Decimal Adder Memory Cell Power Consumption Read Operation Read-write Voltage Table Lookup Write Operation
Content Type	Text
Resource Type	Article
Subject	Control and Systems Engineering Electrical and Electronic Engineering

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
6	Contents and Copyright Issues	Queries related to content curation and copyright issues	content@ndl.gov.in
7	National Digital Library of India Club (NDLI Club)	Queries related to NDLI Club formation, support, user awareness program, seminar/symposium, collaboration, social media, promotion, and outreach	clubsupport@ndl.gov.in
8	Digital Preservation Centre (DPC)	Assistance with digitizing and archiving copyright-free printed books	dpc@ndl.gov.in
9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in

Design and evaluation of a memristor-based look-up table for non-volatile field programmable gate arrays

Low leakage techniques for FPGAs

Area and power efficient decimal carry-free adder

A Novel Design Method for Resolver-to-Digital Conversion

Efficient digit-serial modular multiplication algorithm on FPGA

Efficient ASIC and FPGA Implementation of Binary-Coded Decimal Digit Multipliers

A Cost-Efficient Look-Up Table Based Binary Coded Decimal Adder Design

A Dynamically Reconfigurable Pixel Processor System Based on Power/Energy-Performance-Accuracy Optimization

Single-configuration fault detection in application-dependent testing of field programmable gate array interconnects

Low-power and area efficient binary coded decimal adder design using a look up table-based field programmable gate array

Similar Documents

Design and evaluation of a memristor-based look-up table for non-volatile field programmable gate arrays

Low leakage techniques for FPGAs

Area and power efficient decimal carry-free adder

A Novel Design Method for Resolver-to-Digital Conversion

Efficient digit-serial modular multiplication algorithm on FPGA

Efficient ASIC and FPGA Implementation of Binary-Coded Decimal Digit Multipliers

A Cost-Efficient Look-Up Table Based Binary Coded Decimal Adder Design

A Dynamically Reconfigurable Pixel Processor System Based on Power/Energy-Performance-Accuracy Optimization

Single-configuration fault detection in application-dependent testing of field programmable gate array interconnects

Low-power and area efficient binary coded decimal adder design using a look up table-based field programmable gate array