NDLI: Low leakage techniques for FPGAs

Content Provider	IEEE Xplore Digital Library
Author	Lodi, A. Ciccarelli, L. Guerrieri, R.
Copyright Year	1966
Abstract	Reconfigurable architectures are well suited for wireless applications since they provide high performance computation together with the capability to adapt to changing communication protocols. Moving to 90-nm technology and below, FPGAs could suffer from leakage energy consumption due to the large number of inactive transistors. This paper presents an extensive study on the application of different low-leakage techniques to the design of FPGAs. The approaches are compared and mixed to find an implementation of switch blocks and look-up tables which reduces leakage without affecting delay and area. The circuits we propose achieve an 86% stand-by energy saving and 46% active leakage reduction with respect to standard implementations. The FPGA delay is not affected, while area is increased by only 3%
Sponsorship	IEEE Solid-State Circuits Society IEEE Electron Devices Society IEEE Circuits and Systems Society Japan Society of Applied Physics (JSAP) IEEE Microwave Theory and Techniques Society IEEE San Francisco Section Bay Area Council Univ. PA IEEE
Starting Page	1662
Ending Page	1672
Page Count	11
File Size	538197
File Format	PDF
ISSN	00189200
Volume Number	41
Issue Number	7
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2006-07-01
Publisher Place	U.S.A.
Access Restriction	One Nation One Subscription (ONOS)
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Field programmable gate arrays Energy consumption Switches Computer architecture Wireless application protocol Delay Reconfigurable logic Leakage current Circuits Table lookup switch block Field programmable gate array (FPGA) leakage look-up table (LUT) power
Content Type	Text
Resource Type	Article
Subject	Electrical and Electronic Engineering

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