NDLI: Efficient digit-serial modular multiplication algorithm on FPGA

Content Provider	IET Digital Library
Author	Pan, Jeng Shyang Song, Pengfei Yang, Chun Sheng
Abstract	For cryptographic applications, such as DSA, RSA and ECC systems, the crypto-processors are required to perform modular multiplication (MM) on large integers over Galois field. A new digit-serial MM method is presented by using a variable size lookup table. The proposed modular multiplier can be designed for any digit-size d and modulus M which only requires simple operations such as addition and shifting. Based on theoretical analysis, the efficient digit-serial MM architecture requires the latency of O ( ⌈ n / d ⌉ + d + 2 ) clock cycles. As a result, the developed architecture can achieve less area–delay product on hardware when compared with previous designs.
Starting Page	662
Ending Page	668
Page Count	7
ISSN	1751858X
Volume Number	12
e-ISSN	17518598
Issue Number	Issue 5, Sep (2018)
Alternate Webpage(s)	https://digital-library.theiet.org/content/journals/iet-cds/12/5
Alternate Webpage(s)	https://digital-library.theiet.org/content/journals/10.1049/iet-cds.2017.0300
Journal	IET Circuits, Devices & Systems
Publisher Date	2018-03-28
Access Restriction	Open
Rights Holder	© The Institution of Engineering and Technology
Subject Keyword	Algebra Cryptographic Application Cryptography Cryptoprocessor Digit-serial MM Method DSA System ECC System Efficient Digit-serial Modular Multiplication Algorithm Field Programmable Gate Array FPGA Galois Field Logic And Switching Circuit Logic Circuit RSA System Table Lookup Variable Size Lookup Table
Content Type	Text
Resource Type	Article
Subject	Control and Systems Engineering Electrical and Electronic Engineering

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