NDLI: High-throughput and compact FFT architectures using the Good

Content Provider	IET Digital Library
Author	Bhagat, Nikhilesh Valencia, Daniel Alimohammad, Amirhossein Harris, Fred
Abstract	This study presents two hardware architectures for the efficient implementation of fast Fourier transform (FFT) based on the combined Good–Thomas and Winograd Fourier transform algorithms. The combined algorithms require fewer multiplications compared with the other FFT algorithms by eliminating twiddle factor multiplications. Two hardware architectures are presented: one is a fully-pipelined architecture using multi-dimensional Chinese remainder theorem for a high-throughput implementation and the other is a time-multiplexed architecture, which utilises the folding transformation for the compact realisation of short-length Winograd Fourier transforms. Both designs are fully-parameterisable and have been verified against their synthesisable Verilog descriptions. The characteristics and the implementation results of the two hardware architectures on a Xilinx field-programmable gate array are presented. To the best of the authors' knowledge, this study presents the first hardware realisation of FFT based on the combined Good–Thomas and Winograd FFT algorithms. The application of the proposed FFT architectures in the physical layer of the long-term evolution wireless standard is discussed.
Starting Page	1011
Ending Page	1018
Page Count	8
ISSN	17518628
Volume Number	12
e-ISSN	17518636
Issue Number	Issue 8, May (2018)
Alternate Webpage(s)	https://digital-library.theiet.org/content/journals/iet-com/12/8
Alternate Webpage(s)	https://digital-library.theiet.org/content/journals/10.1049/iet-com.2017.0837
Journal	IET Communications
Publisher Date	2018-02-06
Access Restriction	Open
Rights Holder	© The Institution of Engineering and Technology
Subject Keyword	Combined Good-Thomas And Winograd Fourier Transform Algorithm Compact FFT Architectures Fast Fourier Transform Folding Transformation Fully-pipelined Architecture Function Theory And Analysis Hardware Architectures High-throughput FFT Architectures Integral Transforms Long-term Evolution Wireless Standard Mathematical Analysis Multidimensional Chinese Remainder Theorem Short-length Winograd Fourier Transforms Synthesisable Verilog Descriptions Time-multiplexed Architecture Twiddle Factor Multiplication Elimination Xilinx Field Programmable Gate Array
Content Type	Text
Resource Type	Article
Subject	Electrical and Electronic Engineering Computer Science Applications

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4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
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