NDLI: Single bit-line 8T SRAM cell with asynchronous dual word-line control for bit-interleaved ultra-low voltage operation

Content Provider	IET Digital Library
Author	Huang, Chi Ray Chiou, Lih Yih
Abstract	This study proposes a single bit-line and disturbance-free static random-access memory (SRAM) cell for ultra-low voltage applications. SRAM cell with read-decoupled and cross-point structure addresses both the read-disturb and half-select stability issues; nevertheless, the write-ability is degraded due to the stacked pass transistors. In this study, the authors propose a single-ended 8T bit-cell and dual word-line control technique that can simultaneously improve the read stability, half-select stability, and write-ability without additional peripheral circuits, which is advantageous for bit-interleaved ultra-low voltage operations. A 4 kb test chip was implemented in a 90 nm complementary metal–oxide–semiconductor process to verify the proposed design. Silicon measurements indicate that the proposed design can operate at a voltage as low as 360 mV with 2.68 μW power consumption.
Starting Page	713
Ending Page	719
Page Count	7
ISSN	1751858X
Volume Number	12
e-ISSN	17518598
Issue Number	Issue 6, Nov (2018)
Alternate Webpage(s)	https://digital-library.theiet.org/content/journals/iet-cds/12/6
Alternate Webpage(s)	https://digital-library.theiet.org/content/journals/10.1049/iet-cds.2018.5150
Journal	IET Circuits, Devices & Systems
Publisher Date	2018-08-13
Access Restriction	Open
Rights Holder	© The Institution of Engineering and Technology
Subject Keyword	Asynchronous Dual Word-line Control Asynchronous Machine Bit-interleaved Ultra-low Voltage Operation CMOS Integrated Circuit Control Engineering Computing Control of Electric Power System Digital Circuit Design, Modelling And Testing Dual Word-line Control Half-select Stability Ingle-ended 8T Bit-cell Integrated Circuit Design Low Power Electronics Machine Control Memory Circuit Metal–oxide–semiconductor Process Power System Control Random-access Memory Cell Read Stability Semiconductor Storage Single Bit-line 8T SRAM Cell SRAM Chips Ultra-low Voltage Write-ability
Content Type	Text
Resource Type	Article
Subject	Control and Systems Engineering Electrical and Electronic Engineering

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
6	Contents and Copyright Issues	Queries related to content curation and copyright issues	content@ndl.gov.in
7	National Digital Library of India Club (NDLI Club)	Queries related to NDLI Club formation, support, user awareness program, seminar/symposium, collaboration, social media, promotion, and outreach	clubsupport@ndl.gov.in
8	Digital Preservation Centre (DPC)	Assistance with digitizing and archiving copyright-free printed books	dpc@ndl.gov.in
9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in

Charge sharing write driver and half-VDD pre-charge 8T SRAM with virtual ground for low-power write and read operation

Reliable write assist low power SRAM cell for wireless sensor network applications

Single bit-line 11T SRAM cell for low power and improved stability

A Single-Ended Disturb-Free 9T Subthreshold SRAM With Cross-Point Data-Aware Write Word-Line Structure, Negative Bit-Line, and Adaptive Read Operation Timing Tracing

A Differential Data-Aware Power-Supplied (D$^{2}$AP) 8T SRAM Cell With Expanded Write/Read Stabilities for Lower VDDmin Applications

Low-power data encoding/decoding for energy-efficient static random access memory design

A 40-nm Sub-Threshold 5T SRAM Bit Cell With Improved Read and Write Stability

Ultra Low-Energy SRAM Design for Smart Ubiquitous Sensors

Hetro8T: power and area efficient approximate heterogeneous 8T SRAM for H.264 video decoder

Single bit-line 8T SRAM cell with asynchronous dual word-line control for bit-interleaved ultra-low voltage operation

Similar Documents

Charge sharing write driver and half-VDD pre-charge 8T SRAM with virtual ground for low-power write and read operation

Reliable write assist low power SRAM cell for wireless sensor network applications

Single bit-line 11T SRAM cell for low power and improved stability

A Single-Ended Disturb-Free 9T Subthreshold SRAM With Cross-Point Data-Aware Write Word-Line Structure, Negative Bit-Line, and Adaptive Read Operation Timing Tracing

A Differential Data-Aware Power-Supplied (D$^{2}$AP) 8T SRAM Cell With Expanded Write/Read Stabilities for Lower VDDmin Applications

Low-power data encoding/decoding for energy-efficient static random access memory design

A 40-nm Sub-Threshold 5T SRAM Bit Cell With Improved Read and Write Stability

Ultra Low-Energy SRAM Design for Smart Ubiquitous Sensors

Hetro8T: power and area efficient approximate heterogeneous 8T SRAM for H.264 video decoder

Single bit-line 8T SRAM cell with asynchronous dual word-line control for bit-interleaved ultra-low voltage operation