NDLI: Design and analysis of wideband low-power LNA for improved RF performance with compact chip area

Content Provider	IET Digital Library
Author	Pandey, Sunil Gawande, Tushar Inge, Shashank Pathak, Abhijeet Kondekar, Pravin N.
Abstract	Here, a wideband low-noise amplifier (LNA) based on the two-stage cascade configuration is presented to improve the radiofrequency (RF) performance. With the common gate (CG) input stage, the proposed LNA provides wideband input matching, while the wideband gain response was achieved using the peaking inductors inserted at the drain terminals of each stage. With a standard 0.18 μ m CMOS process, the chip area of the proposed wideband LNA is only 0.116 mm2. However, it consumes a 5.4 mW power from a supply voltage of V dd = 1 V . From the post-layout simulation results, it achieves maximum power gain S 21 of 11.13 dB at 8.5 GHz, input return loss S 11 below −9.44 dB, reverse isolation S 12 less than −60 dB, and small group delay variation of ±97 ps across 8.5–20 GHz frequency range. Moreover, noise figure (NF) lies in the range of 2.19–3.23 dB, whereas the NF minimum ( N F min ) varies in the range of 1.55–2.91 dB for 8.5–20 GHz frequency range. Apart from this, the proposed LNA achieves an IIP3 of 0.96 dBm, when a two-tone test is performed with a frequency spacing of 50 MHz.
Starting Page	1816
Ending Page	1820
Page Count	5
ISSN	17518725
Volume Number	12
e-ISSN	17518733
Issue Number	Issue 11, Sep (2018)
Alternate Webpage(s)	https://digital-library.theiet.org/content/journals/iet-map/12/11
Alternate Webpage(s)	https://digital-library.theiet.org/content/journals/10.1049/iet-map.2018.0055
Journal	IET Microwaves, Antennas & Propagation
Publisher Date	2018-04-24
Access Restriction	Open
Rights Holder	© The Institution of Engineering and Technology
Subject Keyword	Amplifiers Analogue Circuit Design CMOS Analogue Integrated Circuit CMOS Integrated Circuit CMOS Process Common Gate Input Stage Drain Terminals Field Effect MMIC Frequency 8.5 GHz to 20 GHz Improved RF Performance Input Return Loss Integrated Circuit Design Layout Low Noise Amplifier Low Power Electronics Microwave IC MMIC Amplifiers Modelling Modelling And Testing Noise Figure Noise Figure 2.19 DB to 3.23 DB Peaking Inductors Post-layout Simulation Power 5.4 MW Radiofrequency Performance Reverse Isolation Loss Semiconductor Integrated Circuit Design Size 0.18 Mum Small Group Delay Variation Testing Two-stage Cascade Configuration Voltage 1 V Wideband Amplifiers Wideband Gain Response Wideband Input Matching Wideband Low-noise Amplifier Wideband Low-power LNA Analysis Wideband Low-power LNA Design
Content Type	Text
Resource Type	Article
Subject	Electrical and Electronic Engineering

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