NDLI: Harmonic-free and low cost delay-locked loop with a 20

Content Provider	IET Digital Library
Author	Wei, Xing Chen, Zhujia Li, Wei Yang, Haigang
Abstract	A low-cost two-step delay locked loop (DLL) with a 20–80% input duty cycle is presented. For eliminating harmonic and zero-trap locking issues along the whole range of digital controlled delay line, a hierarchy phase detector (HPD) is proposed to compare the phase difference between input reference clock and two phase-isotonic clocks generated by sharing a common delay line. By monitoring of HPD's output, state controller can solve harmonic and zero-trap locking issues while being naturally immune to the wide range of input duty cycle. With an asymmetric edge combiner, high duty cycle correction accuracy can be achieved. The proposed DLL is implemented in 55 nm CMOS technology with a 0.00574 mm2 chip area. Simulation results show that the operation range of the proposed DLL is 0.3–1.6 GHz without the occurrence of harmonic and zero-trap locking, and the range of input duty cycle is 20–80%. The power consumption is 0.76 mW at 1.6 GHz.
Starting Page	70
Ending Page	71
Page Count	2
ISSN	00135194
Volume Number	53
e-ISSN	1350911X
Issue Number	Issue 2, Jan (2017)
Alternate Webpage(s)	https://digital-library.theiet.org/content/journals/el/53/2
Alternate Webpage(s)	https://digital-library.theiet.org/content/journals/10.1049/el.2016.3032
Journal	Electronics Letters
Publisher Date	2016-12-08
Access Restriction	Open
Rights Holder	© The Institution of Engineering and Technology
Subject Keyword	Asymmetric Edge Combiner CMOS Digital Integrated Circuit CMOS Integrated Circuit CMOS Technology Delay Line Delay Lock Loops Demodulator Digital Circuit Digital Controlled Delay Line Discriminators And Mixers DLL Frequency 0.3 GHz to 1.6 GHz Harmonic-free Delay-locked Loop Harmonic-trap Elimination Harmonics Suppression Hierarchy Phase Detector High Duty Cycle Correction Accuracy HPD Output Monitoring Input Duty Cycle Input Reference Clock Low-cost Two-step Delay Locked Loop Microwave IC Modulator Phase Detector Power 0.76 MW Pulse Circuit Size 55 Nm State Controller Two Phase-isotonic Clocks UHF Integrated Circuit Zero-trap Locking Elimination
Content Type	Text
Resource Type	Article
Subject	Electrical and Electronic Engineering

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