NDLI: 2 × VDD output buffer with 36.4% slew rate improvement using leakage current compensation

Content Provider	IET Digital Library
Author	Wang, C. C. Tsai, T. Y. Lee, T. J. Ruan, K. W.
Abstract	A 2 × VDD output buffer using leakage current compensation is demonstrated. With the proposed leakage current compensation circuit, the SR (slew rate) is improved 36.4–101.89% based on on-silicon measurement results given different VDDIO (1.0/1.2/1.8 V) and temperatures (from 0 to 100°C). The data rate is 510/630/400 MHz for VDDIO at 1.8/1.2/1.0 V, respectively. Moreover, the reliability problem, the gate oxide overstress and the hot carrier degradation is avoided. The proposed design is implemented using a typical 90 nm CMOS process. The active area is 0.425 × 0.0563 mm. The SR is measured in the range from 0.766 to 2.585 V/ns.
Starting Page	62
Ending Page	64
Page Count	3
ISSN	00135194
Volume Number	53
e-ISSN	1350911X
Issue Number	Issue 2, Jan (2017)
Alternate Webpage(s)	https://digital-library.theiet.org/content/journals/el/53/2
Alternate Webpage(s)	https://digital-library.theiet.org/content/journals/10.1049/el.2016.2351
Journal	Electronics Letters
Publisher Date	2016-12-01
Access Restriction	Open
Rights Holder	© The Institution of Engineering and Technology
Subject Keyword	Buffer Circuit CMOS Integrated Circuit CMOS Process Compensation Frequency 400 MHz Frequency 510 MHz Frequency 630 MHz Gate Oxide Overstress Hot Carrier Degradation Hot Carriers Integrated Circuit Reliability Leakage Current Leakage Current Compensation On-silicon Measurement Output Buffer Reliability Reliability Problem Slew Rate Improvement Temperature 0 DegC to 100 DegC Voltage 1 V Voltage 1.2 V Voltage 1.8 V
Content Type	Text
Resource Type	Article
Subject	Electrical and Electronic Engineering

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